SU1661862A1 - Device for analysis of transient process - Google Patents

Abstract

The invention relates to instrumentation engineering and can be used to control the dynamic parameters of various control objects when building information measuring systems, in particular, to control the timing parameters of the operation of electromagnetic switching devices (EMCA). The purpose of the invention is to improve the accuracy of parameter determination due to the possibility of analyzing both the front and rear edges of the transient process. The device allows to control the process of operation of the ECMA by the steepness of the voltage rise during the transient process. The monitoring is carried out both in the process of switching on and in the process of switching off the ECA. To prevent false triggering, the device contains a threshold element. 2 Il.

Description

The invention relates to instrumentation engineering and can be used to control the dynamic parameters of various control objects in the construction of information measuring systems, in particular, to control the timing of the operation of electromagnetic switching devices.

The purpose of the invention is to improve the accuracy of parameter determination due to the possibility of analyzing both the leading and trailing edges of the transient process.

Figure 1 presents a diagram of the device: figure 2 - timing diagrams reflecting the operation of the device.

The device (Fig. 1) contains an input bus 1, an output bus 2, a first comparator 3, a second comparator 4, five resistors 5-9, a first and a second bipolar transistors 10 and 11, which differentiate the circuit 12,

the threshold element 13, the field effect transistor 14, in addition, the resistors 5 and 6 form the voltage divider 15. The input bus 1 is connected to the input of the differentiating link 12 and the input of the threshold element 13, the output of which is connected to the output of the differentiating link 12, with the direct input of the first comparator 3 and the direct input of the second comparator 4. The output of the first comparator 3 is connected to the emitter of the first transistor 10 and through the resistor 8 is connected to the base of the second transistor 11. The output of the second comparator 4 is connected to the emitter of the second transistor 11, through the resistor 7 is connected to the base of the first transistor 10, and through the voltage divider 15 to the common bus of the device. The inverting input of the first comparator 3 is connected to the output of the voltage divider 15, and the inverting input of the second comparator 4 is connected to the common bus of the device. The collectors of transistors 10 and 11 are interconnected and

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through a resistor 9 is connected to the output bus 2. The gate of the transistor 14 is connected to the input bus 1, the source of the transistor is connected to the output bus 2, and the drain is connected to the common bus of the device.

The device works as follows.

If there is no voltage on bus 1, the field-effect transistor 14 closes the output bus 2 to the common bus of the device and therefore the voltage Uwyh is zero for any state of Comparators 3 and 4.

When voltage is applied to bus 1 at time ti, transistor 14 is locked, a voltage proportional to the voltage rise UBX appears at the output of differentiator 12, which causes a high voltage level at the output of comparator 4. At divider 15, the voltage setting Dyer, which corresponds to a certain speed (slope) of the input signal and is chosen so that at time ti is less than the voltage at the output of the differentiating circuit 12. Thus, at the time ti and the comparator output 3 is formed a high voltage level.

At the time of T2, the rate of increase in voltage of UBX decreased or became negative (Fig. 1, dashed line).

From time point n to time point t2 at the output of comparators 3 and 4, the voltage has a high positive level, transistors 10 and 11 are closed and there is no voltage on the output bus 2. When the voltage rise steepness decreases at time t2 on bus 1, the voltage on the non-inverting input of comparator 3 is less than the voltage on its inverting input, so a negative voltage is formed at the output of comparator 3, as a result of which transistor 11 becomes saturated and on output bus 2 the leading edge of the pulse is formed.

At time ta, the steepness of the input voltage on bus 1 increases and a positive voltage is generated at the output of the comparator 3, which blocks the transistor 11, and the voltage on the output bus 2 becomes equal to zero, the back edge of the output pulse is formed.

At time t4, the voltage on bus 1 has reached the unopening value of Unop of threshold element 13 and the comparator 3 is kept in a state in which a high positive voltage is maintained at its output.

In the absence of the threshold element 13, while reducing the steepness of the voltage UBx on the input bus 1, a false pulse (dotted line) would be formulated on the output bus 2.

At the time ts, the voltage UBx on bus 1 begins to decrease. At time te, this voltage is less than the voltage of the unlocking of the threshold element 13 and the voltage at the non-inverting input of the comparator 3 is determined by the sign and decay rate of the voltage UBX. When the voltage drops UBX the output voltage

5 of the differentiating circuit 12 has a negative polarity, and a voltage of negative polarity also forms at the output of the comparator 4. Since the decreasing steepness of the voltage is greater than the value of the 0 given value

divider 15, then at the output of the comparator 3

negative voltage present

polarity, and on the output bus 2 no.

At time t, the slope decreases.

5, the voltage has become less than a predetermined value, at the output of the comparator 3 and the output bus 2 a positive voltage is formed (the leading edge of the output pulse). At the moment ta the steepness of the decline

Voltage 0 increased and the trailing edge of the output pulse was formed on the output bus.

At time tg, the amplitude of the output voltage has decreased so much

5 that the field effect transistor 14 was opened and the output bus 2 was shunted.

Thus, the proposed technical solution forms the output voltage when the rise slope increases.

0 voltages both at the leading edge of the UBX voltage, and at the back edge. This makes it possible to control, for example, electromagnets not only at the time of being turned on, but also at the time of being turned off.

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Claims (1)

Claims An apparatus for analyzing a transient process comprising an input and output bus, a differentiating circuit, a resistor, 0 comparator, characterized in that, in order to improve the accuracy of parameter determination due to the possibility of analyzing both the leading and trailing edges of the transition process, four 5 resistors, two bipolar transistors, a field-effect transistor, a threshold element, a second comparator, the first and second resistors being connected in series, the output of the first comparator is connected to the emitter of the first transistor, and through the third resistor is connected to the base of the second transistor, through these series-connected resistors connected to the common bus of the device, the threshold element is connected in parallel to the differentiating circuit, the input of which is connected to the output bus and to the gate of the field-effect transistor, the table of which is connected to the inverter input of the first comparator and connected with the common bus device, and the output of the differentiating circuit is connected to 0 the direct inputs of the first and second comparators, with the inverting input of the second comparator connected to the connection point of the first and second resistors between themselves, and the output of the second comparator connected to the emitter of the second transistor and via the fourth resistor communicating with the base of the first transistor through the fifth resistor is connected to the source of the field-effect transistor and to the output bus. 6 15 naa 13 H s tt, % t i L 6 15 g vsh 1 I m q t i i i 4-j