SU1660017A1 - Device for object testing - Google Patents

Description

The invention relates to computing and can be used to assess the technical condition of the controlled object and predict the time of its withdrawal for prevention. The purpose of the invention is to simplify the device by reducing the information capacity of the drive. The device contains a switch, a normalizer, an ADC, a drive, two setting factors, two multiplication blocks, two accumulating adders, three AND elements, a setting reference, an adder, an indicator, a clock generator, a frequency divider and a shift register. The essence of the invention lies in the fact that the value of the current parameter for which the estimated and extrapolated values are calculated is sequentially recorded in the shift register. The introduction of the shift register makes it possible to reduce the information capacity of the drive by 1_-t of memory cells, where ί is the number of controlled objects; t is the number of controlled parameters. 3 il.

The invention relates to automation and computing and can be used to assess the technical condition of the controlled object and predict the time of its withdrawal to prevention.

The purpose of the invention is to simplify the device by reducing the requirements for the information capacity of the drive.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - diagrams of synchronization of the operation of the device blocks.

The device contains the inputs of 1 object, switch 2, the normalizer 3, analog-to-digital converter (ADC) 4, drive 5, the first unit of the 6 coefficients, the first block 7 multiplication, the first OC

rolling adder 8, first AND 9 element, second setting unit 10 of coefficients, second multiplication unit 11, second accumulating adder 12, second AND 13 element, setting unit of 14 standards, adder 15, third AND 16 element, indicator 17, 18 pulse generator, divider 19 frequency and 20 shift register.

The device works as follows.

The generator 18 and the divider 19 perform the functions of the device synchronizer. The synchronizer generates signals {A} = Αι. Ar, ... Ah, where ί is the number of objects; (C) = MF, Cr ..... Art. where m is the number of controlled parameters: {5} = 5ι. Zg, 5h,

that set the sequence of information processing and synchronize the work. IV Ζ100991

3

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that device nodes. Switch 2 performs sequential polling of sensors measuring the parameters of b objects of control. The switch consists of 1_ tp electronic selection circuits, which receive signals from sensors, polling control signals {A}, {C}, and synchronization signals 5ι. The normalizer 3 performs the presentation of various electrical quantities of the monitored parameters of objects and a certain voltage scale and is implemented on an operational amplifier with a variable gain. The gain of the amplifier is automatically set by control signals {A}, {C} in the interval of the signal $ 1. The gain change is made by switching resistors in the feedback circuit of the amplifier. A / D converter 4 converts the voltage from the output of the normalizer to a digital binary code.

The device operates in real time, cyclically with a polling period of objects T _o . The control of the parameter object sets is implemented using the time division principle.

The drive 5 records and stores the values of the last (-1) measurements for each of the t parameters of all ί control objects. Thus, the drive must have an information capacity of at least k / t (Ν -1) of memory cells. To calculate the estimated and extrapolated parameter values by the method of a fixed sample size used in this device, however, not the last measurements for each parameter are required (Ν - 1), but N. To limit the specified information capacity of the drive, the device is additionally entered the shift register 20 connected to the drive. The shift register has a bit width equal to the bit width of any drive cell and serves to record and store one number — the measurement result in digital form. If binary numbers of different bit width are used to represent the measurement results for different parameters, then the drive cells may also have a different bit depth. Then the shift register must have a bit width equal to the maximum bit width of the cell.

The interaction of the drive with the shift register and with other blocks is as follows. Let at some point in time (see Fig. 3) the measurement results for each of the parameters of all Ϊ control objects be stored in (Ν -1) drive lines.

the last (Ν -1) polling periods of objects To. When in the ADC 4 the next “th” dimension by the) parameter is formed, then under the action of the sync signal 5ι the contents of the corresponding cell of the “1” ruler of the drive 5 are rewritten to the shift register 20, the contents of the analogous cell of the “2” ruler are rewritten into the “G” ruler etc. Under the action of the same clock signal 5, the number from ADC 4 is copied to the corresponding cell of the (Ν - 1) line of drive 5. At the end of the transient processes associated with the census of information, under the action of the clock signal 5g, the contents of the shift register 20 and all accumulator cells The values related to the monitored parameter are given to blocks 7 and 11 to calculate estimated and extrapolated values for this parameter. As you can see, these blocks are given by the N last measurements from the monitored parameter. The selection of the "necessary" drive cells related to the monitored parameter is made using the signals (A} and {C}. After calculating the values of C and 0) 3 the contents of the shift register 20 are reset. With the advent of a new dimension in another controlled parameter, all processes are repeated. Thus, the introduction of a shift register for storing one word allows significantly (on! _- gp cells) to reduce the storage capacity of the drive.

In block 11 and the adder 12, the estimated value of the parameter параметра] is calculated in accordance with the expression

ΰ ₁ = βι and _q ι = Γν; ) = ΰλ (1)

1 = 1

where N is the sample size (number of measurements);

Ιίη is the result of the Ιth dimension) of the parameter;

3 | - The coefficient for evaluating the result of the 1st dimension.

In block 7 and the adder 8, the extrapolated value of the 1-parameter is calculated in accordance with the expression

C] e = §. Ao CC; I = 1Λ !; ) = ΰή (2) 1 = 1

where E | e is the extrapolation coefficient of the result of the 1st dimension.

The values of the coefficients a | and ai for

every 1st dimension is calculated

based on expressions

five

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5.2Ν-2 ³¹ 7 Ν + 1) Ν

3 [(Ν + 2) (Ν + 3) - 2ί (4Ν + 7) + 10? ]

Ν (Ν - 1 -) (Ν -2)

To record and store coefficients

a | and a | e are used as setting devices 10 and 6, respectively, which perform the functions

semi-permanent memory with a capacity of N words each.

In the third adder 15, the values and signs of deviations Δ of the monitored parameters 11] from their nominal values (standards) are calculated [in].

Δ] = ό] -υ _Η ]. (h)

The values of nominal values and κι are stored in the setting unit of 14 standards and Lo to the signals (A) and {C} of the frequency divider 19 are output to the adder 15. The setting unit of the standards is a permanent storage device with a capacity of 1_ - hp memory cells.

In the cycle, the estimated value of the parameter 0] from the output of the adder 12 through the element I 13 is output to the adder 15, where in accordance with the expression (3) is compared with its reference value in], by reading the setting unit 14.

The extrapolated value of the parameter 0] e from the output of the first adder 8 through the element 9 is transmitted to the indicator 17, where it is stored, converted into analog form and in the next cycle is transferred to the display. In this cycle, through the element 16 and on the indicator 17, the value Δ | is taken, which is displayed after a similar conversion.

Simultaneously with these values, the boundaries of the permissible value of the parameter, formed in

the indicator itself 17.

Claims (1)

Claim A device for controlling objects that contains a switch, a normalizer, an analog-to-digital converter, a drive, the first factor adjuster, the first multiplication unit, the first accumulating adder, the first AND element, the second factor setting unit, the second multiplication unit, the second accumulating adder, the second AND element, the setting device standards, the adder, the third element And, the indicator, the generator of clock pulses and the frequency divider, and the switch, the normalizer and 10 analog-to-digital converter are connected in series, the output of the analog-to-digital converter is connected to the information input of the drive, the first information output of which is connected to the first inputs of the first and second multiplication units, the output of the first coefficient setting unit, the output of the second setpoint device coefficients 20 is connected with the second input of the second multiplication unit, the output of which is connected to the input of the second accumulating adder, the output of which is connected to the input of the second lementa AND, whose output is connected to the first 25 by the input of the adder, the second input of which is connected to the output of the master of standards, the output of the adder is connected to the input of the third element I, the output of which is connected to the first input of the indicator, the output of the first multiplication unit is connected to the input of the first accumulating adder ·, A ^ the stroke of which is connected to the second input of the indicator, the output of the clock pulse generator 35 is connected to the input of the frequency divider, the control inputs of which are connected to the synchronous inputs of the switch, normalizer, analogue center digital converter drive, the first and second 40 sets of coefficients, elements And from the first to the third, setters of standards and indicator, the switch inputs are device inputs, characterized in that, in order to simplify the device so as to reduce storage capacity requirements, a shift register is entered into it, the second information output of the drive connected to the information input of the shift register, the output of which is connected to the third inputs of the first and second multiplication units, the control output of the frequency divider is connected to the synchronous input of the shift register. 1660017 1 'l, X = T == 2 ~ 1 _._______ Π _γ L ~ ......____...- ΓΞΖΖ'ΣΖΖΞΞΙ ____ 1_ ^: D * ........ _________-__ Χ == 1_ ( And DG. .. ·, · ..-. Γ ~ Ί _____- About .___ ΣΧζ β ϊ _Ι — I —____ ΓΞΊ -, _— ί With _p _-Έ ± 3 ___ □ ______ £ = □ _ι SHSYP-L π-Π- .11, -.- 0 .___ η_α_ο_α__, ^ (£, B, Shch20) -Π Π ---. .Π ,, Π — 0-П__ □ Π Π π π π π π. η π π π π, 1 16Y0017