SU1658393A1 - Device for separating signals arriving from two directions - Google Patents

Abstract

The invention relates to communication technology and can be used in duplex signal transmission systems. The aim of the invention is to improve the noise immunity of the device. The device comprises a matching unit 1, a switch 2, a digital-to-analog converter (DAC)

Description

The invention relates to communication technology and can be used in duplex signal transmission systems.

The aim of the invention is to improve noise immunity.

FIG. 1 shows a block diagram of a device for separating signals from two directions; in fig. 2 is a block diagram of a storage unit of a device for separating signals from two directions.

A device for separating signals of two directions contains a matching unit 1, a first switch 2, a first digital-to-analog converter 3, an analog-digital converter 4, a shaper 5 code combinations, a memory block 6, a control pulse generator 7, a subtractor 8, an adder 9, a second digital-to-analog converter 10, second switch 11, first buffer register 12, attenuator 13, first shift register 14, second shift register 15, main memory unit 16, second buffer register 17, setup input 18, information input 19, you water 20 and the output 21 of the device for the separation of signals of two directions, the output 22 of block 6, the input 23 of the adder 9, the input 24 of the subtractor 8, the input 25 of the buffer register 12.

A device for separating signals from two directions works as follows.

A link is connected to pin 20. The operation process can be divided into two stages: the process of preliminary adaptation of the device to the parameters of the communication channel (the learning process) and the process of duplex information transfer. The learning process is as follows. Immediately after switching on the device, all blocks that can store information (memory block 6 and buffer register 12) are nullified. Then, the signal from the terminal equipment to the setup input 18 receives a logical zero. On this signal, the switch 2 connects the output of the imager 5 to the input of the digital-to-analog converter (DAC) 3; the switch 11 connects the output of the analog-to-digital converter (ADC) 4 to the input 25 of the buffer register 12; block 6

the memory is transferred to the position at which from its output 22 the code combination arrives at the input of the adder 9 corresponding to the zero signal. Shaper

5 alternately (in accordance with the signals arriving at its input from generator 7), in binary form, gives the code combinations corresponding to the values (counts) of all used to represent

signal source message levels: x0,

Xl x2 xihp, x0 .. which are cyclically

are repeated. These samples are fed to the input of the DAC 3, in which they are converted to analog form, and then the analog signal

enters the input of the ADC 4 and the communication channel. In addition, the ADC 4 also receives from the communication channel a reflected signal, the value of which is determined by the impulse response of the communication channel. From the output of the ADC 4

the digital signal y (kT) is fed to the input of the subtractor 8 and through the switch 11 to the input 25 of the buffer register 12, from the output of which the digital signal y (k-1) T, recorded in it during the previous

(k-1) -ro learning tact. This signal in the attenuator 13 with the transmission coefficient C decreases in amplitude by a factor of 10 and is fed to the input 23 of the adder 9. As the other input of the adder 9 receives the output

22 of the block 6 code combination corresponding to the zero signal, the signal from the input 23, without changing its value, is fed to the input 24 of the subtractor 8.

At the output of the subtractor 8, a difference signal is generated between the current and the previous values of the response of the communication channel CCT) (kT) - -Sy (k-1) T. which is recorded in memory block 6 at an address determined by a combination of two binary numbers, the first of which is a set of digital samples of the signal at the input of the DAC 3 {x (kT) x (k-1) T., x (k-Mi ), and the second is a set of digital samples of the signal at the output of the attenuator 13 {Cy (k-1) T Су (k-2) T ... Cy (k-M2) T}, where ML M2 is the number of signal samples, respectively at the input of the DAC 3 and the output of the attenuator 13. taken into account when forming the address.

For example, if Mi is 2, Mg 1 x (k-1) T | - 101. x (kT) 100, Su (k-1) T 111 (resolution of the ADC and DAC g 3), then the first binary number that determines the address of the memory block 6 - & (kT) x ( k-1) {100101}, and the second number is {111}. When implementing block 6, these military numbers can be interpreted either as a row address and a column address, or as one military number, the bit of which is equal to the sum of the two numbers, i.e. in this case, {100101111}. Simultaneously with the recording of the signal in the memory block 6, the current value of the signal y (kT) is recorded in the buffer register 12. At that, the learning process ends.

It should be noted that after the completion of the learning process, the counting value of the signal y (IT) is stored in the buffer register 12. written to it in the last one. 1st, training pace.

After learning from the signal of the terminal equipment, a logical unit arrives at the installation input 18 of the device, and the device switches to the duplex information transfer mode. At that, the switch 2 connects the output of matching unit 1 to the input of the DAC 3, and the switch 11 connects the output of adder 9 to the input 25 of the buffer register 12, and the generation of the zero signal at output 22 of block 6 also stops. The samples of the information input signal x (t) from the output of the message source are fed to the information input 19 of the device, and in the flea 1 the matching is converted into a digital form x (kT). The input of the ADC 4 simultaneously receives signals from the output of the DAC 3 and the signals from pin 20 (on the opposite side of the channel) z (t). The total signal is converted into ADC 4 into a digital form y (kT) + z (kT) and is fed to the input of the subtractor 8. From buffer register 12, a count of the signal y (IT) is recorded, recorded there at the last 1st learning cycle and, being reduced , by amplitude at times in attenuator 13, is fed to input 23 of adder 9, to another input of which output 22 of memory block 6 receives counting of a difference signal (CCT), read from a memory cell whose address is determined by a combination of two decimal numbers, showing the levels of the signals x (k T) x (k-1) T ... x (k-Mi) T and Cy (k-1) T Cy (k-2) T ... Cy ( k-mz) t. At the output of the adder 9, a signal 5 (kT) L (kT) + Cy (gp y (kT) - Cy (k-1)) is generated. Since the previous beat was the last training beat, i.e., k - 1 I, the output of the adder 9 produces a signal whose value is equal to the magnitude of the response

the communication channel at the k-th moment of the preamble: S (kT) - cy (kT). The signal S (kT) is then fed to the input 24 of the subtractor 8. where it compensates for the reflected signal coming from the channel

connection. The output of the subtractor 8 produces a signal KkT) y (kT) + z (S (kT) - y (kT) + z (y (kT) -z (kT)), i.e., the information signal from the opposite side of the channel is restored communication. At the end

0 k-ro clock signal from the output of the adder 9 is written to the buffer register 12, and the difference signal z (kT) from the output of the subtractor 8 is fed to the DAC 10, where it is converted to analog form and fed to the output 21

5 devices.

Thus, in this device, there is a separation of the signals of the two directions of transmission x (t) and the reception of z (t) without introducing distortions into the signals. The use of a recursive signal processing algorithm allows to reduce the required memory size and, therefore, to implement a device with high noise immunity.

5 The purpose of the attenuator 13 is to ensure the stability of the recursive circuit: the output of the adder 9 is the input of the switch 11 — the input 25 of the buffer register 12 — the input of the attenuator 13 — the input 23 of the adder 9.

0 Due to the presence of an attenuator 13, the error in the digital representation of the signals is also reduced.

Memory unit 6 operates as follows.

5 In the device learning mode, the installation inputs of the RAM block 16 and the buffer register 17 are given a logical zero signal, by which the buffer register 17 is reset during the entire time that this signal is present, and the RAM block 16 is set to the write mode The information inputs of shift registers 14 and 15 are received from the first and second address addresses of memory block 6, respectively, with code combinations of signals x (kT) x (k + 1) T ... x (k + Mi-1)) T. Cy (k + M2-2) T. These samples are recorded in registers 14 and 15, respectively, which are serial-parallel registers. The signals recorded in registers 14 and 15 are address signals for the RAM block 16 and are fed to its first and second address inputs, respectively.

5 After the address has been generated, a signal arriving at its information input is recorded in the RAM block 16. From the output of the memory block 16, the signal goes to the information input of the buffer register 17. However, the latter, as

It has been indicated above that during the learning process it is continuously nullified and, therefore, a null code combination is present at its output. Upon completion of the learning process, the installation input of the memory block 6 receives a logical unit signal, by which the RAM block 16 is switched to the read mode, and the buffer register 17 is set to a state in which the information signal is not fixed in it, and passes to the output 22 blocks b,

Thus, in the device the matrix organization of memory is used. The values Mi and Mg determine the length of registers 14 and 15 respectively, taking into account the parameters of the impulse response of the communication channel connected to the device. With increasing Mi and M2, the accuracy of the digital representation of the communication channel responses increases, although the required memory capacity of the block 16 increases. At the same time, if certain optimal Mionr and M2opt values are exceeded, the accuracy of the communication channel response representation does not increase. The results of simulation simulation of the effect of a device on a computer have shown that it is advisable to choose Mi, M2 within 2-4.

The use of the device allows duplex data transmission with high noise immunity, reduces the impact on the quality of information transmission of echo signals in long-distance telephone channels, and improves the stability of conference communication systems by eliminating electro-acoustic feedback between sound sources and receivers. .

Claims (2)

1. A device for dividing two-direction signals, comprising a serially connected matching unit, a first switch, a first digital-to-analog converter, an analog-to-digital converter and a subtractor, a setup input of a memory unit connected to a setup input of the first switch whose output is connected to the first address input the memory block, the output of which is connected to the first input of the adder, the output of the control pulse generator is connected to the control inputs of the memory block, analog-digital conversion ers, and the shaper block matching codewords, the output of which is connected to the second input of the first switch and the memory information input unit connected to the input of the second digital to analog the converter, the output of which is the output of the device for separating the signals of two directions, the setup input, the information input and the output of which are respectively the installation input of the memory unit, the input of the matching unit and the output of the second digital-to-analogue converter, characterized in the second switch, the first buffer register and the attenuator, whose output is connected to the second address input of the memory unit and to the second input, are introduced in series of noise immunity; ummatora whose output is connected to the second input of the subtractor and the first input of the second switch, the second input and the installation input of which are connected respectively to the output of the analog-digital converter and the installation input the memory block, the output of the control pulse generator is connected to the control input of the first buffer register, the output of the subtractor is connected to the information input of the memory block. 2. The device pop. 1, characterized in that the memory block contains the first and second shift registers, the RAM block and the second buffer register, the first address inputs of the RAM block are connected respectively to the outputs of the first shift register, the second address the inputs of the RAM block are connected respectively to the outputs of the second shift register, and the output of the RAM block is connected to the information input of the second buffer register, the output of which is the output of the memory block, the information inputs of the first second and second shift registers and block RAM are respectively the first and second address and information inputs of the memory block, the control inputs of the first and second shift registers, the RAM block and the second buffer register are combined and are the control input of the memory block, the installation input of which is the installation input of the RAM block connected to the installation the input of the second buffer register 2