SU1658389A1 - Device for residue forming according to random number modulus - Google Patents

Abstract

The invention relates to computing and can be used in digital computing devices. The purpose of the invention is to increase speed. The device for forming the remainder of an arbitrary module contains the input 1 of the device number, the input 2 of the device module, the output 3 of the device residue, the OR 4 element, the encoder 5, the matrix multiplicity determining nodes 6, the group subtractors 7, the matrix elements AND 8, the OR elements 9 groups, the decoder 10, the output 11 of the device termination, the inputs 12 constants of the device group 1 or fe O 00 00 00

Description

The invention relates to computing and can be used in digital computing devices.

The aim of the invention is to increase speed.

The drawing shows a functional diagram of the device for forming a remainder in an arbitrary modulus of the number.

The device contains the input 1 of the device number, the input 2 of the device module, the output 3 of the device residue, the element OR 4, the encoder 5, the matrix multiplicity determination nodes 6, the group subtractors 7, the matrix elements AND 8, the elements of group OR 9, the decoder 10, the output 11 of the end devices, inputs 12 constants of the device group.

The essence of the invention is that in order to form the remainder ak modulo PI from the number Ak, at the same time, the codes of numbers from one to the maximum value of the modulus Pmax, reduced from the unit, from which the formation of the remainder, the results Si Si,

S. Ak-1Sp Ak- (Rmax-1) limit

meanings

 }} S1-S | Pl € {Pi. Rmax},

of which, by simultaneously checking the multiplicity of the module Pi, choose

Sj 6 {Si, SiHfcj 0, mod Pi.

At the same time ak ak - sj.

According to the example of the structure of the device.

For example, if a device forms residues modulo PI 23, P2 17, Pz 7, P / 1 5, RB 3, then the matrixes of the multiplicity-6 nodes and the And 8 elements must contain five columns, and the first should be twenty three corresponding elements, seven in the second, seven in the third, five in the fourth, and three in the fifth. The group of elements OR 9 consists of seventeen elements. The group of subtractors 7 consists of twenty two subtractors. The nodes of the matrix column multiplicity determination implement the function of determining the multiplicity of the number Ac to its given module PI, if, for example, the modulus seven multiplicity determination function is implemented, then the algorithm for their operation will be described by the expression:

Y1 X WX.lX4Xfi ... Xi; | VX 1Х2ХЗХ / 1ХТ ,. “Q v V-Х1Х2ХЧХ.1ХГ). Xi | v / x lX2X3X 1Xt: i. X. | i.

where q is the input resolution 1. to hot ppreddeksch maximum value mch pp dk.

The device works as follows.

The PI 6 {Pi, Pmax} module, according to which it is necessary to form the remainder of a given number, is given by a parallel binary code supplied to input 2. This parallel binary code is numerically equal to the value (number) of the specified module. Input 1 is affected by the binary code of the number Ak in the parallel code. The code of the module Pi, entering the inputs of the decoder 10, is decrypted on it. Therefore, at one of the outputs of the decoder, uniquely corresponding to the code of the PI module, a signal of a logical unit appears, which arrives at the second inputs of the AND elements of the 8th column, in which the multiplicity determination nodes 6 implement the multiplicity determination function of the Pi module, which ensures the implementation of the function

(Si. Si} 3 Si S, - Pi6 {Pi. Pmax}.

At the same time, the code of the number Ak is supplied to the inputs of the subtractors 7 and to the combined inputs of the nodes 6 for determining the multiplicity of the first row. The outputs of the subtractors 7 form the numbers S2 Ak - 1Sp Ak - (Rmax - 1). which arrive respectively at the combined inputs of the nodes b of the definition of the multiplicity of subsequent lines. Therefore, in each column there is a twist on the multiplicity of the numbers {Si.Sj}. (i 2, P) to its given module P. At the outputs of those nodes 6, where

VSjЈ {Sp, Si} f, mod Pi (f {Pi. Pmax),

the unit potentials in ts, which are fed to the first inputs of elements of AND 8. At that, only that element of 8. 8 will work. The second input of which receives the resolving potential from the output of the decoder 10, and the first from the output of node 6, for which it turned out fulfilled the condition:

SjЈ {Si. Si} g S, sO, mod P, i. .

The signal from the output of the element AND 8 through the element OR 9 is fed to the input of the encoder 5, which implements the function of encoding the number ak and to the input of the element OR 4. In this case, the output of the encoder is a combination of ones and zeros of the binary code ak AK - Sj, and output element 4, a signal appears to indicate the end of the process of forming a residue.

Let us consider an example of a specific implementation of the process of forming the remainder in an arbitrary modulus of a number. Let the device implement the process of forming residues modulo PI 23, PZ 17, Pz 7, PA 5, PS 3. It is necessary to form ak with Ax - 1238 and P | 17.Then, in the column of nodes 6, which implement the function of determining the multiplicity according to PI 17, at the expense of subtractors 7, codes of numbers from 1238 to 1222 are received. Therefore, from the output of node 6 of the fifteenth row (1224 sO, mod 17), 8 and OR 9 the signal of a logical unit is fed to the fourteenth input of the encoder 5, which ensures the formation at its output of the code of the number of ac ak -Sj 1238-1224 14.

Claims (1)

The invention The device for forming the remainder in an arbitrary module of the number containing the element OR, the decoder, the first subtracter of the group, the first and second elements of the OR group, the units determining the multiplicity of the first and second rows of the matrix, the elements of the first and second rows of the matrix, and the input number of the device connected to the input of the decremented first subtractor of the group, the input of which is subtracted is connected to the first input of the constants of the device group, the outputs of the multiplicity determination nodes of the first and second rows of the matrix are connected respectively These are the first inputs of the first and second rows of the matrix, the outputs of the elements And the first row of the matrix are connected respectively to the inputs of the first element OR of the group, the outputs of the elements AND the second row of the matrix are connected respectively to the inputs of the second element OR of the output of the first and second elements OR of the group with the corresponding inputs of the element OR, the input of the device module is connected to the input of the decoder, the outputs of which are connected to the second input i With the corresponding elements of AND of the first row of the matrix, the output of the first subtractor of the group is connected to the inputs of the multiplicity determination nodes of the second row of the matrix, t is characterized in that, in order to improve speed, it contains an encoder, from the second to (ni - 1) -th ( ni is the maximum value of the module) of the subtractors of the group, from the third to A2-th (n2-next largest, after the maximum, value of the module) OR elements, from the third to the ni-th (ni - 1st value of the module, I 1 - t, t - the number of values of the module) the nodes of the definition of the multiplicity of the 1st column of the matrix retigo by n-th elements AND 1st column of the matrix, and the input of the device number is connected to the inputs of the multiplicity determination nodes of the first row of the matrix and to the inputs of the decremented subtractors from the second to (n-1) -th group, the inputs of which are subtracted are connected to the corresponding inputs the device group constants, the k-ro output of the group subtractor (k - 2 - (u-1) is connected to the inputs of the multiplicity determination nodes (k + 1) -th row of the matrix, the outputs of the multiplicity determination nodes (k + 1) -th row of the matrix are connected with the first inputs of the corresponding elements And (k + 1) -th row of the matrix, the outputs of the decoder are connected to the second inputs of the AND elements, except the first, the corresponding columns of the matrix, the outputs of the AND elements of the Jth row of the matrix (J 3-P2) are connected respectively to the inputs of the j-ro element OR group, the output of the J-ro element OR group Connected to The jth input of the OR element, the output of which is the output of the end of the device, the output of the remainder of which is connected to the output of the encoder, the output of the 1st element AND of the first column of the matrix (I - П2 + 1 - ш) is connected to the lth input of the OR element, the outputs of the elements OR, except the first, the group and the outputs from (n2 + 1) -th to pgy elements And the first column of the matrix are connected respectively to the inputs of the encoder.