SU1656670A1 - Operational amplifier - Google Patents

Description

The invention relates to radio engineering. The purpose of the invention is to improve the static characteristics without sacrificing speed and linearity in the large signal mode.

The operational amplifier uses an input push-pull differential cascade 1, made with two anti-phase high-resistance outputs and asymmetry. The invention relates to radio engineering and can be used to process electrical signals with high speed and accuracy in systems with limited power supply.

The purpose of the invention ~ improvement of static characteristics without degrading performance and linearity in the large signal mode.

Figure 1 presents the structural electrical circuit of the proposed operational amplifier (OA) according to claim 1 of the claims; Fig 2 shows a possible variant of its specific implementation.

The OS contains a push-pull differential cascade 1, a small signal amplification channel 2 and an output adder 3. A small signal amplification channel 2 is provided on a two-way limiter 4. a resistor 5, an inverting amplifier 6 with a capacitor in the feedback circuit and a voltage-current converter 7.

2

with a high-impedance output. A small signal amplification channel 2 was inserted, containing a two-way limiter 4, a resistor 5, an inverting amplifier 6 with a capacitor in the feedback circuit, and a voltage-to-current converter 7. The small signal channel 2 amplification allows to provide an artificial low signal mode in a number of stages of the operational amplifier and at the same time ensure its good linearity in the large signal mode and good parameters on the direct current, since in the output adder 3, the linear components of the signal are summed up in any mode . 1 Cp. Χ ly, 2 ill. ι

with

with

The input push-pull differential cascade 1 is performed on the first, second, third, fourth, and fifth transistors 8.

9, 10, 11 and 12 of one type, on the sixth, seventh and eighth transistors 13. ί4 and 15 of a different type, on the first, second and third controlled current sources 16, 17 and 18. On the first and second resistors 19 and 20, on bias source 21 and bias element 22,

The proposed OU works as follows.

It consists of two signal transmission channels, however, unlike the well-known two-channel amplifiers, at the input of each channel in which the frequency separation of the signal is made, in the proposed op-amp this separation is not performed, and the output signals are not multiplied, as in most known devices, but are summed up . The contribution of each channel in result 1656670 A1

3

1656670

four

The output output depends on the mode in which the op-amp operates.

Suppose that a small signal is present at the input of an opamp. This condition is typical for the case when the OS operates without feedback at low frequencies or with feedback in a balanced mode.

Suppose that there is no feedback, the amplitude of the signal at the output of the opamp is 1 V. If the voltage gain of the small signal channel 2 together with the differential amplifier at transistors E, 9 is, for example, 10 ⁵ , then the signal applied to the inputs of the op-amp, in this case is equal to 10 mV. The gain of the input push-pull differential cascade 1 is usually 200-300. Consequently, in the mode in question, the signal at the output of this channel (for example, in the prototype) would be only 2-3 mV, which is 0.2-0.3% of the signal at the output of the small signal channel 2. In the same proportion, the currents entering to the input of the output adder 3. Therefore, in the small signal mode, the contribution of the input push-pull differential cascade 1 to the resulting gain can be neglected. Accordingly, its small-signal errors can be neglected, with such OU characteristics as DC gain and common-mode attenuation coefficient (COSS), are fully determined only by the small signal channel 2 together with transistors 8, 9, and the resulting input shift is determined exclusively the degree of consistency of these transistors. At the same time, in terms of static precision, the proposed OU is not inferior to any known amplifiers made on

same technological level.

Using the frequency of the input signal, the amplification of the low-signal channel 2 is reduced, which is due to the parallel feedback capacitance, which covers the inverting amplifier 6, however, it remains larger than the input two-terminal differential stage 1 up to the cut-off frequency of its own frequency response, later due to resistor 5 the gain of the low signal channel 2 begins to decrease at a speed of 12 dB / oct and becomes negligible compared to the gain of the input push-pull differential stage 1. In this case, starting with a certain frequency, the total gain is determined almost exclusively by this cascade.

When switching to a large signal mode, for example, when the OS is turned on with a non-inverting voltage follower and a pulse-front transmission, the signal is also amplified only by the input push-pull differential stage 1, which has an extremely high relative speed and linearity in the large signal mode. This is due to the significantly greater gain from the inputs of the opamp to the antiphase high-resistance outputs of the input push-pull differential stage 1 compared to the gain at high frequencies of the small signal channel 2, which therefore does not affect the transmission of short fronts.

However, at the moment of switching on the asymmetrical output of the input push-pull differential stage 1, there is also a large signal that is fed to the input of the small signal channel 2, and since the current from the output of this channel is summed with the output currents of the input push-pull differential stage 1, when a small signal channel 2 hits the nonlinear he would equally determine the magnitude and nature of the distortion of the output signal, but not at the front, but at the top of the transmitted pulse. To eliminate the influence of the small signal channel 2 on the nature of the transmission of signals having a high slew rate, it is necessary to implement this channel in order to prevent nonlinear distortions of its output current at any slew rate of the signal at the input of an opamp. This condition is met by using a double-sided limiter 4, a limiting signal on the asymmetrical high-resistance output of the input two-contact differential cascade 1 to level 1) _o , and a resistor L of resistance H. It is obvious that with the introduction of these elements into the small signal channel 2, the input current of the inverting amplifier 6 cannot exceed the values of Ho / P. This decision practically doesn’t affect the low-signal characteristics of the low-signal channel 2, but πρ · τ guarantees a linear amplification mode of the inverting amplifier 6 at any rate of rise of the signal at the input of the op-amp if the initial bias current of this stage is chosen greater than and / ₀ . However, the condition under which the signal current of the cascade always has a smaller value compared with the initial current of its displacement, and there is a condition for the low-signal amplification mode.

Therefore, the proposed technical solution allows to provide an artificial low-signal mode in a number of OU stages and at the same time to ensure its good linearity in the larger signal mode and good parameters at a constant current, since in the output adder 3 when the OU operates in any mode

five

1656670

6

only linear components of the signal are summed. To implement this structure, the OS should additionally fulfill one more condition. Since the output of the inverting amplifier 6 cannot be directly connected to the auxiliary input of the adder 3, which would shunt the low output impedance of this amplifier to the symmetrical anti-phase outputs of the two-contact differential stage 1 and its malfunction, there is a converter between the output of the inverting amplifier 6 and the input of the output adder 3 voltage-current 7. One of the variants of its specific implementation is shown in figure 2.

As an output adder 3, either a simple connection of the outputs of the small signal channel and the input two-stage differential stage 1 can be used, as shown in Fig. 2, or a cascade with ON, the input of which summarizes the signal from one of the anti-phase high-resistance outputs of the two-stage differential stage 1 and the output signal of the small signal channel 2. In this case, the signal from another anti-phase high-impedance output can arrive at the summation point either directly or also through a cascade with ON. The use of such cascades allows us to somewhat improve the frequency properties of the OU by reducing the capacitance value reduced to the OU output.

Claims (2)

Claim 1. An operational amplifier containing an input push-pull differential cascade made with two anti-phase high-resistance outputs and an output adder, while the anti-phase high-resistance outputs of the input push-pull differential cascade are connected to the corresponding inputs of the output adder, characterized in that, in order to improve the static characteristics without deterioration speed and linearity in the large, signal mode, the input push-pull differential cascade is made with an unbalanced high-resistance output m, the adder output is configured with additional input and entered the small-signal gain channel comprising a double-sided limiter, a resistor, an inverting amplifier with a capacitor in the feedback circuit and the voltage-current converter, the asymmetrical high-resistance output of the input two-stroke differential cascade is connected via a serially connected double-sided limiter and resistor to the input of an inverting amplifier, whose output through the voltage converter is connected to the auxiliary input of the adder. 2. The amplifier according to claim 1, that is, that the input push-pull differential cascade contains first, second, third, fourth and fifth transistors of one type, sixth, seventh and eighth transistors of another type, The first second and third controlled current sources, the first and second resistors, the bias source and the bias element, while the bases of the first and second transistors are formed by the non-inverting and inverting inputs of the push-pull differential cascade, the base of the sixth and seventh transistors are connected respectively o to the bases of the first and second transistors, the emitters of the third and fourth transistors, respectively, through the first and second resistors are connected to the emitters of the sixth and seventh transistors, and the bases to the first output of the bias source, the inputs of the first and second controlled current sources are connected through the bias element and connected to collectors of the sixth and fourth transistors, respectively, and their outputs are connected respectively to the second and first terminals of the bias source, the second terminal of which is connected to the emitters of the first and second The fifth and eighth emitters of the transistors are connected to the corresponding power supply buses, their bases are to the inputs of the first and second Yuka controlled sources, respectively, and their collectors are the corresponding antiphase high-resistance outputs of the two-stage differential cascade, and the collectors of the third and seventh transistors are connected to the corresponding source buses power supply, and the collectors of the first and second transistors are connected respectively to the input and output of the third controlled source As a current, the collector of the second transistor is an asymmetrical high-resistance output of the input push-pull differential stage. 1656670 figure 1 Fig.?