SU1653143A1 - Pulse delay and frequency doubling device - Google Patents

Abstract

The invention relates to a pulse technique, can be used as part of digital electronics devices, and allows to obtain time-delayed pulses that accurately preserve the time parameters of the input pulse, as well as receive double-frequency pulses at the leading and trailing edges of the input pulse, the duration of which is the same . To do this, the device containing the first and second elements EXCLUSIVE OR, the output of the first is connected to one input of the second, the other input of which is connected to the input bus, an inverter is additionally introduced, the output of which is connected to the cathode of the newly inserted diode, the anode of this diode is connected to the first input of the first an EXCLUSIVE OR element and one lining the time of the master capacitor, the second lining of which is connected to another input of the same element. 2 Il. with Ј (L

Description

The invention relates to a pulse technique and can be used as part of digital electronic equipment devices.

The purpose of the invention is to increase the delay time, the accuracy of the parameters of delayed pulses and double frequency pulses.

Aa FIG. 1 shows a circuit diagram of a pulse delay and frequency doubling device; in fig. 2 - time diagrams of his work.

The device contains the first and second 1.2 EXCLUSIVE OR elements, the output of the first is connected to the first input of the second element, the second input of which is connected to the input bus 3, also connected to the input of the inverter 4, the cathode of diode b, the anode of which is connected to the first input of the element EXCLUSIVE OR 1, the second input of which is connected to the anode of the diode 6, the cathode of which is connected to the output of the inverter 4. The time setting capacitor 7 is connected between the inputs of the EXCLUSIVE OR element 1. The output of the EXCLUSIVE OR element 2 is connected to the output bus 8 delayed by it pulse, and the output of the EXCLUSIVE OR gate is connected to one output line 9 of double frequency. The first and second inputs of the EXCLUSIVE OR 1 element are connected to the power source through resistors 10 and 11, respectively.

ABOUT

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with

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with

The device works as follows.

The front edge of the input pulse on the bus 3 (Fig. 2, Uj) sets a low potential at the output of the inverter 4. Diode 5 is shifted in the opposite direction, diode 6 is in the forward direction, as a result, the capacitor is charged by the input outflow current of the first input of the EXCLUSIVE OR 1 element (Fig. 2, where U, X (corresponds to the potential at the first input of the EXCLUSIVE OR element 1, U , Vu2. To the potential at the second input of the element EXCLUSIVE OR 1).

During the interval t - t. the capacitor is charged and a positive potential grows on its bottom plate. Until t, this potential corresponds to a low level at the input, and since the other input is also low, then according to the element EXCLUSIVE OR element algorithm, the output EXCLUSIVE OR 1 will have a low potential at the output (bus 9) (Fig. 2, U ,)

At time t s, the potential of the first input of the EXCLUSIVE OR element 1 reaches the threshold U, above which the potential will correspond to a high level. Therefore, a high potential is established on tire 9 in the interval

Tt

When forming the back front

the input pulse from the time t (Fig. 2, U, B) (d) diode 5 is shifted in the forward direction, and diode 6 in the opposite direction. As a result, the capacitor 7, previously charged with a positive potential on the bottom plate, is recharged in the opposite direction, and the potential of the second input of the EXCLUSIVE OR element 1 increases (Fig. 2, U1BX4). Perezar occurs on the circuit: power supply - the second input of the EXCLUSIVE OR element 1 - capacitor 7 - diode 5 - input bus 3 - housing. Up to the moment t, the potential of the second “entry of the EXCLUSIVE OR 1 element () corresponds to a low level, and since the first input of the EXCLUSIVE OR 1 element is also low, there will also be a low potential at its output (on the bus 9).

At the moment t, the potential of the upper entrance reaches the threshold U, above which the potential will correspond to a high level. Therefore, on the bus 9

after t. potential is high.

Since the input flowing currents of both inputs of EXCLUSIVE OR 1 are almost equal, the intervals t, - t and t are also equal to each other. These intervals correspond to a low level at the output of the EXCLUSIVE OR 1 element — on bus 9 (FIG. 2, U), and on bus 9, there will be double frequency pulses.

At the inputs of the element EXCLUSIVE OR 2 there are pulses from the output of the element EXCLUSIVE OR 1 and bus 3.

In accordance with the algorithm of the work of the EXCLUSIVE OR 2 element, at its output there will be pulses shown in FIG. 2, U. The leading edge of these pulses is delayed by the interval tj-c, the rear one - by t, and the pulses themselves are inverted relative to the input pulses.

The inputs of the EXCLUSIVE or 1 element can be connected to the power source through resistors 10 and 11, if separate adjustments are required for the delay — the leading or trailing edge of the pulses.

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Claims (1)

Invention Formula A pulse delay and frequency doubling device containing the first and second elements EXCLUSIVE OR, the first input of the second element EXCLUSIVE OR is connected to the input bus, the output of the first element EXCLUSIVE OR is connected to the second input of the second element EXCLUSIVE OR, the time setting RC circuit characterized by In order to increase the delay times and the accuracy of the parameters of the delayed pulse and double frequency pulses, an inverter is inserted into it, the output of which is connected to the cathode of the inserted diode, the anode of the diode is connected to the first the input of the first element EXCLUSIVE OR, the input of the inverter is with the input bus and the cathode of the second input diode, the anode of which is connected to the second input of the first element EXCLUSIVE OR and one plate of the time of the setting capacitor, the second plate of which is connected to another input of the same element.