SU1647644A1 - Device for pulse repetition period measurement in magnetic medium transport checks - Google Patents

Abstract

The invention relates to instrumentation engineering and can be used to control the speed of movement of a mobile information carrier in external memory accumulators. In order to increase reliability, a device for measuring pulse periods, containing a pulse generator, first and second counters, a multiplexer, first and second registers, first, second, third and fourth elements AND, inverter, recorder, first trigger, code bus, triggers are entered second through eighth frequency dividers, two AND-OR elements, third register, modulo two adders, memory block, adder, indicator, three control buses. The device operates in three modes: preparation for measurement, measurement, recording of results. In pre-measurement mode, the memory unit has zeroed. In the measurement mode, the duration of periods is measured by filling them with stable frequency pulses, the distribution of periods by their duration and storing in the memory block a histogram of the distribution of periods by their duration. In the registration mode, the contents of the memory block are entered into the recorder (print, display, plotter, etc.). 1 il. Yo

Description

The invention relates to instrumentation engineering and can be used to control the speed of movement of a mobile information carrier in external memory accumulators.

The aim of the invention is to increase the reliability of the device by drawing up a histogram of the distribution of the periods in the process of change.

The drawing shows a block diagram of the device.

The device contains triggers 1 - 6 with RS-inputs, D-triggers 7, 8, generator 9 pulses, frequency divider 10, elements AND-OR 11,12, elements AND 13-16, inverter 17, counters 18, 19, registers 20 - 22, block

23 modulo-two adders, multiplexer 24, memory block 25, adder 26, recorder 27, indicator 28, code bus 29, single potential bus 30, input pulse bus 31, control buses 32 - 34.

The device operates in three modes: preparation for measurement, measurement, recording of results. Before each of the modes, the device is reset to the initial state by applying an adjusting pulse to the R-inputs of the flip-flops 1 - 3, 6 - 8, counters 18, 19, registers 21, 22,

In measurement preparation mode, memory block 25 is zeroed. Mode starts

ABOUT

4 vj

ABOUT

4 N

By applying a pulse through bus 32, over which trigger 1 is set to one, triggers 2 and 3 remain in the zero state, a non-zero potential is fed to the control input of the multiplexer 24. The outputs of the bits of the counter 19 through the multiplexer 24 are connected to the address inputs of the memory block 25. The register 22 is maintained in the zero state by the output signal from the inverse output of the flip-flop 1, the AND element 16 is closed by the same signal. The zero code from the output of the adder 26 enters the information inputs of the memory block 25.

Each output pulse divider 10, trigger 4 is set to one. The generator pulse 9 unit is entered into the register 20 and is consistently advanced in it. Since the first output pulse of the register 20, the trigger 4 is set to zero, the outputs of the register 20 for each output pulse of the divider sequence form a sequence of eight non-overlapping pulses with a duration equal to the period of the generator 9. The output pulses of the register 20 are designed to control the operation of the device the beginning of the eighth pulse of the register 20, the trigger 5 generates a single control pulse of the block 25. The AND-OR element 12 transmits the sixth pulse of the register 20 to the block enable input 25. For every eighth pulse of the register 20, the content of the counter 19 is increased by one. As a result, zero addresses are recorded at all addresses from 0 ... O to 1 ... 1 in block 25. Upon completion of writing zero at the last address 1 ... 1, a signal is generated at the first output of the counter 19, which sets the trigger 1 to the zero state. The zeroing mode of block 25 is terminated.

The measurement mode starts with the trigger 3 being set to a single state by a pulse on the bus 34. The multiplexer 24 is set to transmit the code from the outputs of block 23 to the address inputs of block 25. To the input of element 16, the enable signal is given, and from input R of register 22 the setting signal is removed signal. The input pulses, the period T between which is measured, over the bus 31 through the element AND-AND-I11 arrive at the D input of the trigger 4. A sequence of eight non-overlapping pulses is formed for each bus pulse 31 in register 20. On the third pulse of register 20, the minimum code NMHH of the period to be registered is written into the counter 18 by an additional code. On the fourth pulse regi

country 20 flip-flop 6 is set to one, opening element i 13, the output pulses of generator 9 are sent to the counting input of counter 18 to the first output pulse of register 20 of the next input pulse on bus 31. elements 7,14, 15 and 17 analyze the period code in the counter 18.

When the counter reaches the number 18 of pulses equal to MM, a single level arrives at the D input of trigger 7 and the corresponding inputs of the elements 14 and 15. The number registered in the lower bits (in relation to the discharge,

5 connected to the D-input of the trigger 7) of the counter 18 at the end of the next period T of the input pulses, is rewritten into the register 21 by the second output pulse of the register 20 arriving at the C-input of the register

0 21 through the element I 15. In this case, the trigger 7 is in the zero state, if the code of the duration of the period T is in the specified tolerance Mmin NI Ymax. At the output of the element And 14 will be zero, and

5 at the output of the inverter 17 - unit. The trigger 8 is set to one by the seventh output pulse of the register 20, generated on the first input pulse of the bus 31. As a result, the passage through the AND 15 pulse of the rewriting pulse to the zero information register 21 is blocked.

the beginning of the first period of TT pulses on the bus 31.

At the zero level at the output of the And 14 element, the output code of the register 21 without change is fed through block 23 and multiplexer 24 to the address inputs of memory block 25. On the third output pulse of the register 20. passed through the element 12

0 to the input of the resolution of block 25, the information from block 25 is reproduced at the address specified by the register 21. This information is recorded in register 22 by the falling edge of the output pulse.

5 of the element 12. In the adder 26, a unit is added to the register code 22 and the code received in the adder 26 is recorded in block 25 at the same address. The code is recorded by triggering pulses of trigger 5 and

0 element 12 is similar to the process of recording a zero code in the previous mode of preparation for measurement. For every eighth output pulse of register 20, register 21 is reset to zero. If the period code is T

5 will be less than the NMHH value, then at the end of this period, the D-input of the trigger 7 and the corresponding inputs of the elements 14 and 15 will be zero. Items And 14 and 15 will be closed. The zero register code 21 through block 23 and multiplexer 24 enters

to the address input of block 25. At the zero address, the code from block 25 is reproduced and the code value increased by one in the adder 26 is again recorded at the zero address in block 25.

If the period code is LI8x. then after setting the unit at the D input of the trigger 7, the trigger 7 is set to the one state by a signal at the C input. At the output of the element And 14 is set to a single level, and at the output of the inverter

17 is zero. Element 15 prohibits the pulse to write code to register 21, and the zero code remains in it after resetting by the eighth pulse of register 20 in the previous cycle. If there is a single level at the output of the element And 14, the block 23 inverts the zero code of the register 21, the unit code in all bits goes to the address inputs of the block 25. Next, there is an increase by a unit of information at this address.

As a result, at the end of the measurement mode, the number of periods with values exceeding Mmin by the value from 0 ... 01 will be recorded at each address from 0 ... 01 to 1 ... 10 of block 25. 1 ... 10 respectively. At the address 0 ... 0, the number of periods with the values Ni NMMH will be recorded. and at the address 1 ... 1 the number of periods with NI 2 values will be written: Mmax.

The end of the measurement mode is carried out after the end of the analysis of a specified number of M periods, which is counted in the counter 19, or after the end of the burst (if there are skips in the burst), when the number of period pulses in the counter 18 after the last input pulse on the bus 31 exceeds set limits, or overflow of the memory capacity of the block 25 in one of the addresses when the transfer pulse of the adder 26 sets the indicator 28 (for example, a trigger with a display element) to one about In this case, the pulse from the second counter output

18 or from the third output of the counter 19, or from the output of the indicator 28 sets the trigger 3 to the zero state.

The results recording mode starts with a pulse through bus 33 to the input of trigger 2, which is set to one and allows the pulses of the divider 10 to pass through the AND-OR 11 element to the input of trigger 4. Register 20 generates a sequence of eight control pulses through each output pulse of the divider 10. Outputs

The counter bits 19 are connected via multiplexer 24 to the address inputs of memory block 25. The information in the counter 19 is sequentially changed from 0 ... O to 1 ... 1 eighth

the output pulses of register 20 generated by each output pulse of divider 10. As a result, the output information of block 25 successively as the addresses increase from 0 ... O no 1 ... 1 is reproduced on the third output pulse of register 20, is written to register 22 and transmitted to the recorder 27. Since the write enable pulse in block 25 is blocked by the AND-OR 12 element, the information in

In block 25, registration is not overwritten, but remains unchanged after the end of registration. If necessary, the registration process may be repeated several times. Each registration cycle

ends with the zero setting of trigger 2 by the output pulse of counter 19.

25

Claims (1)

Invention Formula A device for measuring pulse periods during monitoring the movement of a magnetic carrier, comprising a pulse generator, the output of which is connected to one input of the first element, the other input of which is connected to the output of the first trigger, and the output is connected to the counting input of the first counter, second counter, outputs of bits which are connected to the first group of multiplexer inputs, the first register, the second register, the bit outputs of which are connected to the recorder, the first input of the second element AND is connected to the first input of the third element And, the second input of which is connected to the output of the inverter, the fourth element is AND, the code bus, characterized in that, in order to increase the reliability, seven second to eighth flip-flops are introduced into it, a frequency divider, two AND-OR elements, a third register, block two modulators, a memory unit, an adder, an indicator, three control buses, which are connected to the first inputs, respectively the second, third and fourth flip-flops, the outputs of which are connected to the first group of inputs of the first AND-OR element, the output of the first AND-OR element is connected to the first input of the fifth trigger, the output of which connected to the information input of the third register, the output of the pulse generator is connected to the clock input of the third register and through the frequency divider to the first and second inputs of the second group the inputs of the first AND-OR element, the third input of the second group of inputs of which is the device input, the first output of the third register is connected to the first input of the first trigger and the second input of the fifth trigger, the second output of the third register is connected to the third input of the third element AND, the third output to control input of the first counter and to one input of the first group of inputs of the second element Y-YLI, the fourth output to the second input of the first trigger, the fifth output to the first input of the sixth trigger, the sixth output to the other input of the first group the second element is AND-OR, the seventh output is to the clock input of the seventh trigger, the eighth move to the second input of the sixth trigger, to the counting input of the second counter and to the installation input of the first register, the information inputs of which are connected to the output group of the first counter, and the outputs are connected to the group of inputs of the block of the accumulator modulo two, the first output of the first counter is connected to the clock input of the eighth trigger, the second output of the first counter - to the information input of the eighth trigger and to the first input of the second element Ora input of which is connected to the output of the eighth flip-flop, and an output connected to the input of the inverter and the other input summato- ra modulo two, the outputs of which are connected to block the second group of inputs of the multiplexer, a fourth flip-flop output connected to the control input of the multiplexer and to the information input of the eighth trigger, whose output is connected to the fourth input of the third element AND, the output of the third element AND connected to the clock input of the first register, the inverse outputs of the second and third triggers are connected to the second group of inputs of the second element AND-OR the output of which is connected to the clock input of the second register and to the resolution input of the memory block, the multiplexer outputs and the outputs of the adder are connected respectively to the group of address and information inputs memory unit, the control input of which is connected to the output of the sixth trigger, and the outputs are connected to the information inputs of the second register, the inverse output of the third trigger is connected to the first input of the fourth And element, and to the installation input of the second register, the outputs of which bits are connected to the input group of the adder , the second input of the fourth element is And is connected to the bus of a single potential, and the output is connected to one input of the adder, one output of which is connected to the input of the indicator, the output of the indicator, the third output of the first account ika and the first output of the second counter group are connected to inputs of the fourth AND gate, the second output of the second counter is connected to the second inputs of the second and third flip-flops, and the coded line is connected to the adjusting inputs of the first counter.