SU1647618A1 - Method for data transmission and device thereof - Google Patents

Abstract

The invention relates to telemechanics and can be used in multichannel geophysical equipment, which converts the measurement into a digital code. The purpose of the invention is not to increase the information content and reliability when receiving information. The method is as follows. The analog signals from the sensors are converted into code pulse sequences that modulate a predetermined pulse sequence in phase, and in turn are transmitted to the communication line. At the receiving side, by phase demodulation of the received L signal, a predetermined pulse sequence is extracted from it and compared to the formed impedance sequence. In the event of a mismatch of two pulse sequences, an information reception error signal is generated. 2 Il. YU

Description

The invention relates to telemechanics and can be operated in a multichannel geophysical instrument, which transforms measurement signals into a digital code.

The purpose of the invention is to increase the information content and reliability when receiving information.

Fig. „1 shows time frames 5 in Fig. 2 — the functional diagram of the device.

The device contains sensors 1 ... ... 1, analog-digital converters 2 4 ... 2 g, switch 3, converter 4 paralenic code to serial, synchronizer 5, phase modulator 6, driver 7 clock pulses, output amplifier 8, lines 9 and 10 of communication, filter 11, amplifier-limiter 12, phase demodulator 13, clock selector 14, synchronizer 15, serial to parallel converter 16, error detection unit 17, registration unit 18, clock pulse generator 19.

The transmission method is as follows.

In the transmitting part, pulses are formed (Fig. 1a) of the frame of transmitted information and a predetermined pulse sequence (Fig. 1C), which

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modulated by a sequential code of information (Fig. 1c). The phase-modulated pulse sequence (Fig. 1d), together with the frame pulses, is converted into a bipolar phase-modulated signal (Fig. Chd), which is transmitted via a communication cable to the receiving part.

In the information signal received with a delay T (Fig. 1e), various distortions are possible due to interference in the communication channel.

After the selection of the frame sync pulses (Fig. 1i), a predetermined pulse sequence (Fig. 1L) begins to form, the frequency of which is equal to the frequency of the predetermined pulse sequence.

From the received information signal (Fig. 1e), at the moments of the last zero crossing, pulses are formed (Fig. Chk), according to which a selected pulse sequence (Fig. 1m) is formed, which is compared bit by bit with formed by a given pulse sequence (Fig, 1l).

In the event of a mismatch between the generated and the received pulse sequences, pulses are generated (Fig. 1H) in the corresponding information code bits, where the reception error has occurred.

The device that implements the method works as follows.

Information from sensors 1 ... 1 signals, the number of which corresponds to the number of measuring channels, after conversion by analog-to-digital converters 24 .... 2 n signals from the sensors is fed to the input of switch 3 in a binary parallel code. From the output of the converter 4 of the parallel code, serial information signals are fed to the input of the phase modulator 6, to the second input of which a specified pulse sequence is fed to the output of the clock generator 7. From the output of the phase modulator 6, the information is fed to the input of the output amplifier 8, to the second input of which synchronization pulses are generated, generated in the synchronizer 5. Bipolar phase-modulated signals are received in the communication link 9, which with delay T and possible

distortions occurring in the communication channel are received in the receiving part, restored, pass through the filter 11 and the amplifier-limiter 12. The sync pulse selector 14 generates frame synchronization pulses according to which a given pulse sequence is formed in the clock pulse generator 19, which is fed to the input of the block 17 error detection, to the other input of which received signals are received (Fig. 1e). In block 17, a predetermined pulse sequence is selected from the received signal and compared with the one formed in the shaper (Fig. 1l). The result of the comparison (Fig. 1H) goes to block 18 along with a parallel binary code information demodulated by a phase demodulator 13 and a converted code sequence to parallel converter 16.

The synchronizer 15 with the receiving part performs synchronous operation of the blocks of the receiving part.

The clock pulse generator 19 is a controlled frequency divider, one input of which is supplied with high-frequency pulses from the output of the synchronizer 15, and the other input - frame synchronization pulses. As a result, a predetermined pulse sequence is formed at its output, which is fed to the input of block 17.

Claims (2)

Formula iso b of e geni A method of transmitting information, consisting in that a synchronization pulse is generated on the transmitting side, analog signals from each sensor are converted into a sequence of binary pulse signals, by means of which a clock pulse sequence is phase-controlled and a synchronization pulse and phase-modulated pulse sequences are transmitted in time , on the receiving side, filtering and limiting the amplitude of the received signals is carried out, then by their phase demo The duplication sequentially extracts from them binary impulse sequences that are recorded, differing in that 51 In order to increase the information content and reliability of the method, at the receiving side, when receiving a synchronization pulse, a control sequence of clock pulses is formed, from the received signals, after their amplitude limitation, a sequence of clock pulses is selected, compared to a control sequence of clock pulses and with a discrepancy in time selected and a control sequence of clock pulses form a reception unreliability signal, 2. A device for transmitting information containing sensors on the transmitting side, the outputs of which are connected to the information inputs of the analog digital converters, the outputs of which are connected to the information inputs of the switch, the output of which is connected to the first input of the parallel code to serial converter, the output of which is connected to the first input a phase modulator whose output is connected to the first input of an output amplifier, the output of which is connected to the first communication line, the second communication line is connected to the input synchronizer, the first and second outputs of which are connected to the control inputs of the analog-digital converters and switch, respectively, the third output of the synchronizer is connected to the second input of the parallel code to serial converter, the fourth output of the synchronizer is connected to the second input of the output amplifier, at the receiving side - a filter whose output through the limiting amplifier is connected to the input of the phase demodulator and the transducer five 0 5 0 Q five 186 the sync pulse selector input, the output of which is connected to the synchronizer input, the first output of which is connected to the second communication line, the first communication line is connected to the filter input and to the second input of the sync pulse selector, the second synchronizer output is connected to the third sync pulse selector input, output of the phase demodule the torus is connected to the first input of the serial to parallel converter, the outputs of which are connected to the first inputs, the registration block, the last to the first input of the error detection block to, the output of which is connected to the second input of the registration unit, the third output of the synchronizer is connected to the second input of a serial to parallel converter, characterized in that, in order to increase the information content and reliability of information transfer, a fifth pulse clock is entered into it on the transmitting side the synchronizer output is connected to the first input of the clock pulse generator, the output of which is connected to the second input of the phase demodulator, the output of the parallel code converter to the last The primary one is connected to the second input of the clock pulse generator, the clock pulse generator is entered at the receiving side, the output is select-. the clock of the clock pulses and the fourth output of the synchronizer are connected respectively to the first and second inputs of the clock pulse generator, the output of which is connected to the second input of the error detection unit, to the third input of which the output of the amplifier-limiter is connected. o -r-ETL. P 5 P. P ... P P .. -P . .... I GL  .PQ b   - --- A -Ax / MvA / n AA  n  iin m Ml I I I III I I I I I I I I I I I I I III LCLQJILD CLELa ELn IlO. / V ± 1П П П ГГП П П П П П П Fig / .a I one