JPS62222730A - Data multiplexing transmitter - Google Patents

Data multiplexing transmitter

Info

Publication number
JPS62222730A
JPS62222730A JP6678486A JP6678486A JPS62222730A JP S62222730 A JPS62222730 A JP S62222730A JP 6678486 A JP6678486 A JP 6678486A JP 6678486 A JP6678486 A JP 6678486A JP S62222730 A JPS62222730 A JP S62222730A
Authority
JP
Japan
Prior art keywords
channel
transmission
circuit
data
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6678486A
Other languages
Japanese (ja)
Inventor
Takeshi Osanai
剛 小山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP6678486A priority Critical patent/JPS62222730A/en
Publication of JPS62222730A publication Critical patent/JPS62222730A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the transmission efficiency in the transmission through one line and to simplify the transmission/reception circuit by multiplexing with time division a pulse whose amplitude is changed in response to a channel and whose width is changed in response to a data and separating a channel from the amplitude of a pulse train signal and obtaining a data level from the pulse width. CONSTITUTION:A transmission circuit is provided with a pulse width modulation circuit 1 and an amplitude adjusting circuit 2 and extracts a pulse train signal subjected to time division multiplexing in response to the width modulation pulse corresponding to 4 channel data and in response to the amplitude corresponding to the channel as a transmission signal. A reception circuit uses comparators 161-164 using voltages VR1-VR4 corresponding to each channel as comparison references to an input through a transmission line 12 so as to discriminate the amplitude. The output of the comparator 161 among the outputs is extracted by a buffer 176 as it is and the outputs of the comparators 162-164 are extracted by exclusive OR circuits 177-179 respectively as channel separation outputs. Then a demodulation output in response to the pulse width is obtained by meaning circuits 181-184.

Description

【発明の詳細な説明】 ん産業上の利用分野 本発明は、チャンネルデータの多重化パルス伝送装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for multiplexed pulse transmission of channel data.

B1発明の概要 本発明は、複数チャンネルのデータを多重化してパルス
伝送する装置において、 チャンネルに応して振#Aを変えかつデータに応じて幅
を変えたパルスを時分割で多重化して送信し、この送信
されたパルス列信号の部幅からチャンネル分離をしかつ
パルス幅からデータレベルを得ることlこより、 1回線tこよる伝送でしかも伝送効率を高めながら送受
信回路を間車化できるようlこしたものである。
B1 Summary of the Invention The present invention is a device that multiplexes data from multiple channels and transmits pulses, in which pulses with varying amplitude #A depending on the channel and width depending on the data are multiplexed and transmitted in a time-division manner. By separating the channels from the part width of the transmitted pulse train signal and obtaining the data level from the pulse width, it is possible to reduce the transmitting and receiving circuits while transmitting over one line and increasing the transmission efficiency. It is strained.

C0従来の技術 従来、チャンネルデータの多重化ノ(ルス伝送には時分
割によって各チャンネルのデータ多重化を行うものが兄
られ、この時分割多重化データ通信にも同期式と非同期
式のものがある。
C0 Conventional Technology Conventionally, channel data multiplexing (multiplex transmission) involves time-division multiplexing of data on each channel, and time-division multiplex data communication also includes synchronous and asynchronous methods. be.

同期式は、データビットの区切りを時間的に識別するた
めのビット同期信号をデータ回線とは別の回線でクロッ
クとして伝送する。非同期式は、データ中tこスタート
、ストップビットの同期情報を含ませて送信し、受信側
で該同期情報からキャラクタの始まりのタイミングを得
ると共にビットの区切りを判定する。
In the synchronous type, a bit synchronization signal for temporally identifying data bit divisions is transmitted as a clock on a line different from the data line. In the asynchronous method, synchronization information of start and stop bits is included in the data and transmitted, and the receiving side obtains the timing of the start of a character from the synchronization information and determines the delimitation of bits.

また、同期式、非同期式共Iこ数チャンネルのデータを
多重化するにはデータ中にチャンネル同期信号を含ませ
、この同期信号からチャンネル分離を行うようにしてい
る。
Furthermore, in order to multiplex data of I channels in both synchronous and asynchronous systems, a channel synchronization signal is included in the data, and channels are separated from this synchronization signal.

D0発明が解決しようとする問題点 従来の多重化伝送によれば、同期式ではデータとクロッ
クの2回線を必要とし、非同期式の場合には1回線で済
むが非同期のため制御が複雑(こなるし実効伝送速ずが
低下する開明があった。
D0 Problems to be Solved by the Invention According to conventional multiplex transmission, the synchronous type requires two lines for data and clock, while the asynchronous type requires only one line, but the control is complicated due to the asynchronous type. There was a discovery that the effective transmission speed decreased.

また、同期式、非同期式共に多重化伝送lこはチャンネ
ル同期信号を含ませることを必要とし、該同期信号の分
離抽出回路などを必要とするし伝送効率を悪くするもの
であった。
In addition, both synchronous and asynchronous multiplexed transmissions require the inclusion of a channel synchronization signal, which requires a circuit for separating and extracting the synchronization signal, resulting in poor transmission efficiency.

1問題点を解決するための手段と作用 本発明は上記問題点条こ鑑みてなされたもので、複数チ
ャンネルのデータを多重化してパルス伝送する装置にお
いて、各チャンネルデータに対応した幅変調パルスをチ
ャンネルEこ対応づけた振幅を持たせて時分割で多重化
した送信回路と、この送信回路から伝送路を介して受信
したパルス列信号のS幅からチャンネル分離しかつパル
ス幅からデータレベルを復調する受信回路とを備え、チ
ャンネルの区別を振幅によって行い、データをパルス幅
によって対応づけた送信と受信を行うものである。
1 Means and Function for Solving the Problems The present invention has been made in view of the above-mentioned problems.In an apparatus for multiplexing data of a plurality of channels and transmitting pulses, the present invention provides a method for transmitting width modulated pulses corresponding to each channel data. A transmission circuit that is time-division multiplexed with amplitudes corresponding to channels E, and channels that are separated from the S width of a pulse train signal received from this transmission circuit via a transmission path, and demodulated from the pulse width to a data level. It is equipped with a receiving circuit, distinguishes channels by amplitude, and transmits and receives data in correspondence with each other by pulse width.

F、実施例 第1図は本発明の一実施例を示す回路図である。F. Example FIG. 1 is a circuit diagram showing an embodiment of the present invention.

送信回路はパルス幅変調回路1と振幅調整回路2とを備
え、4つのチャンネルデータに対応した幅変調パルスを
チャンネルに対応づけた振幅を持たせて時分割で多重化
したパルス列信号を伝送信号として取出す。
The transmission circuit includes a pulse width modulation circuit 1 and an amplitude adjustment circuit 2, and uses, as a transmission signal, a pulse train signal in which width modulation pulses corresponding to four channel data are time-division multiplexed with amplitudes corresponding to the channels. Take it out.

パルス幅変調回路1の構成を説明する。4つのチャンネ
ルCH1〜OH4からのアナログ信号をバッファ3.〜
34で夫々受け、コンパレータ41〜44の夫々の比較
人力にする。クロック発生器5は伝送速度に比例した周
波数のパルスを発生し、三角波発生器6はクロック発生
器5の出力パルスに比例した周波数の三角波を発生する
。一方、分周器7はクロック発生器5の出力パルスを1
/N tC分周し、この分周出力とシフトクロックとす
る4進リンクカウンタ8に三角波発生器6の周波数2位
相をこ一致したシフトパルス(デユーティ 1/4)を
得る。アナログスイッチ9.〜9.はリングカウンタ8
のシフトパルスによって順次オンされ、三角波発生器6
の三角波出力信号を順次取出してコンパレータ41〜4
4の比較基準信号にする。
The configuration of the pulse width modulation circuit 1 will be explained. Analog signals from four channels CH1 to OH4 are buffered 3. ~
34, respectively, and are used as comparative forces for each of comparators 41 to 44. The clock generator 5 generates a pulse with a frequency proportional to the transmission speed, and the triangular wave generator 6 generates a triangular wave with a frequency proportional to the output pulse of the clock generator 5. On the other hand, the frequency divider 7 divides the output pulse of the clock generator 5 into 1
/N tC, and a shift pulse (duty 1/4) with the frequency 2 phase of the triangular wave generator 6 matched is obtained in the quaternary link counter 8 which uses the divided output and the shift clock. Analog switch9. ~9. is ring counter 8
The triangular wave generator 6 is turned on sequentially by the shift pulse of
The triangular wave output signals are taken out sequentially and sent to comparators 41 to 4.
4 as the comparison reference signal.

次Iこ、i#Ax整回路2は、4つのチャンネルfこ対
応づけたレベルの電圧を発生する分圧抵抗1()1〜1
06と、この各電圧点と出力端との間を前述のコンパレ
ータ4.〜44の出力lこよってオン・オフするアナロ
グスイツチ1】、〜11.とによって構成される。この
搦幅g4整回路2の出力パルスは伝送路12を通して受
信回路に伝送される。
Next, the i#Ax rectifier circuit 2 has voltage dividing resistors 1()1 to 1 that generate voltages at levels corresponding to the four channels f.
06, and the above-mentioned comparator 4.06 is connected between each voltage point and the output terminal. The analog switch 1], which is turned on and off by the output l of ~44, ~11. It is composed of The output pulse of the amplitude g4 adjustment circuit 2 is transmitted to the receiving circuit through the transmission line 12.

受信回路は、振幅弁別回路13と、チャンネル分離復調
回路14とを備え、伝送路12を介して受信したパルス
列信号の振幅からチャンネル分離し、分離したパルスか
らデータレベルを復調する。
The receiving circuit includes an amplitude discrimination circuit 13 and a channel separation/demodulation circuit 14, and separates the channels from the amplitude of the pulse train signal received via the transmission line 12, and demodulates the data level from the separated pulses.

振幅弁別回路13の構成を説明する。伝送路12からの
パルス列信号をバッファ15でインピーダンス変喚し、
コンパレータ[61〜16.の共通の比較入力にする。
The configuration of the amplitude discrimination circuit 13 will be explained. The impedance of the pulse train signal from the transmission line 12 is changed by the buffer 15,
Comparators [61-16. common comparison input.

抵抗17.〜17.は各コンパレータ16.〜16!に
チャンネルに対応づけた異なるレベルの比較基準電圧を
与える。
Resistance 17. ~17. is each comparator 16. ~16! Provide comparison reference voltages of different levels corresponding to channels.

チャンネル分離復調回路14は、コンパレータ16゜〜
164の各出力パルスを入力とするバッファ17gと排
他的論理和回路177〜17qと、これらの出力パルス
のパルス幅に比例したアナログ電圧を祷る平均化回路1
81〜184とを備え、平均化回路+8+〜184の出
力iこ4つのチャンネルの復調出力を祷る。
The channel separation demodulation circuit 14 includes a comparator 16°~
164 output pulses as input, exclusive OR circuits 177 to 17q, and an averaging circuit 1 that generates an analog voltage proportional to the pulse width of these output pulses.
81 to 184, and the outputs of the averaging circuits +8+ to 184 are used to demodulate the four channels.

こうした回路構成の動作を第2図及び第3図を参照して
説明する。
The operation of such a circuit configuration will be explained with reference to FIGS. 2 and 3.

送信回路の各部波形は第2図1こ示すようになる。The waveforms of each part of the transmitting circuit are shown in FIG.

4つのチャ/ネルOH1〜OH4の夫々の電圧■1〜v
4に対して、三角波発生器6の三角波出力(第2図I!
L)がアナログスイッチ9.〜9.で順次一周期分取出
され(第2図す、c、d、e)、コンパレータ41〜4
41こよってレベル比較される。これlこよって、コン
パレータ41〜44の出力(第2図f 、 g 、、h
 。
Each voltage of four channels OH1 to OH4 ■1 to v
4, the triangular wave output of the triangular wave generator 6 (Fig. 2 I!
L) is an analog switch 9. ~9. (Fig. 2, c, d, e), and the comparators 41 to 4
41, the levels are compared. Therefore, the outputs of the comparators 41 to 44 (Fig. 2 f, g, h
.

1)Iこはチャンネル磁圧V、−V、に比例した幅のパ
ルスが夫々得られる。そして、コンパレータ4.〜44
の出力fこよってアナログスィッチ111〜114カ順
次オンされることから伝送路12への入力(第2図j)
はパルス幅がチャンネル電圧V、〜v4に一致し、振幅
がチャンネルlこ対応づけられたパルス列信号になる。
1) Pulses with widths proportional to the channel magnetic pressures V and -V can be obtained. And comparator 4. ~44
Since the output f of the analog switches 111 to 114 are turned on in sequence, the input to the transmission line 12 (Fig. 2 j)
becomes a pulse train signal whose pulse width matches the channel voltages V, to v4 and whose amplitude corresponds to the channel 1.

次に、受信回路では第3図に各部波形図を示すように、
伝送路12を通した入力(第3図a)に対して各チャン
ネルに対応づけた電圧VR,〜VR,%比較基準とする
コンパレータ161〜1641こよって振幅弁別がなさ
れ、これらコンパレータ16+ S−164の各出力の
うちコンパレータ16.の出力はそのママバッファ17
cによってチャンネルC」のチャンネル分離出力(第3
図b)として取出され、コンパL/ −夕16゜〜16
4の出力は排他的論理和回路17−r〜1711によっ
てチャンネル分離出力(第3図c、a、e)として取出
される。そして、平均化回路18.〜184において各
チャンネル分離出力の平均化(例えば積分)によってパ
ルス幅に応じた復調出力即ちチャンネル入力電圧■、〜
v4に夫々比例する出力電圧V、〜v4を得る。
Next, in the receiving circuit, as shown in the waveform diagram of each part in Fig. 3,
Amplitude discrimination is performed by comparators 161 to 1641, which serve as voltages VR, ~VR, and % comparison standards, corresponding to the input through the transmission line 12 (FIG. 3a), and these comparators 16+S-164 Of each output of comparator 16. The output of is its mother buffer 17
channel separation output (third
Figure b) is taken out and the comparator L/-16°~16
The outputs of 4 are taken out as channel separation outputs (FIG. 3c, a, e) by exclusive OR circuits 17-r to 1711. And averaging circuit 18. ~184, by averaging (for example, integrating) the separated outputs of each channel, the demodulated output according to the pulse width, that is, the channel input voltage ■, ~
Obtain output voltages V, ~v4, respectively proportional to v4.

なお、実施例1こおいて、各部回路は適宜設計変更しう
るものである。
Note that in the first embodiment, the design of each circuit can be changed as appropriate.

G0発明の効果 以上のとおり、本発明lこよれば、チャンネルlこ応じ
て振幅を変えかつデータに応じて幅を変えたパルスを時
分割で多重化して送信し九これをチャンネル分離と復調
するようにしたため、1回線の伝送路による多重伝送f
こなるし、チャンネル同期信号、ビット同期信号を不要
にして伝送効率、速度を向上できる効果がある。
Effects of the Invention As described above, according to the present invention, pulses with different amplitudes depending on the channel and widths depending on the data are multiplexed and transmitted in a time division manner, and these pulses are separated into channels and demodulated. As a result, multiplex transmission f using a single transmission line
This has the effect of improving transmission efficiency and speed by eliminating the need for channel synchronization signals and bit synchronization signals.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2図は第1
図薔こおける送信側のタイムチャート、第3図は第1図
における受信側のタイムチャートである。 1・・パルス幅変調回路、2・・・振幅調整回路、4I
・・コンパレータ、8・・リングカウンタ、12・・・
伝送路、■3・・振幅弁別回路、14・・・チャンネル
分離復調回路、[6%・・コンパレータ、18.・・・
平均化回路。 第2図 佐福僧19イム(χ−ト
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a time chart of the transmitting side in FIG. 1, and FIG. 3 is a time chart of the receiving side in FIG. 1... Pulse width modulation circuit, 2... Amplitude adjustment circuit, 4I
...Comparator, 8...Ring counter, 12...
Transmission line, ■3... Amplitude discrimination circuit, 14... Channel separation demodulation circuit, [6%... Comparator, 18. ...
Averaging circuit. Figure 2 Sappoku Monk 19 im (χ-t)

Claims (1)

【特許請求の範囲】[Claims] 複数チャンネルのデータを多重化してパルス伝送する装
置において、各チャンネルデータに対応した幅変調パル
スをチャンネルに対応づけた振幅を持たせて時分割で多
重化した送信回路と、この送信回路から伝送路を介して
受信したパルス列信号の振幅からチャンネル分離しかつ
パルス幅からデータレベルを復調する受信回路とを備え
たことを特徴とするデータの多重化伝送装置。
A device that multiplexes data from multiple channels and transmits pulses includes a transmission circuit that multiplexes width modulated pulses corresponding to each channel data in a time-division manner with amplitudes corresponding to the channels, and a transmission path from this transmission circuit. 1. A data multiplex transmission device comprising: a receiving circuit that separates channels from the amplitude of a pulse train signal received via the pulse train signal and demodulates the data level from the pulse width.
JP6678486A 1986-03-25 1986-03-25 Data multiplexing transmitter Pending JPS62222730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6678486A JPS62222730A (en) 1986-03-25 1986-03-25 Data multiplexing transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6678486A JPS62222730A (en) 1986-03-25 1986-03-25 Data multiplexing transmitter

Publications (1)

Publication Number Publication Date
JPS62222730A true JPS62222730A (en) 1987-09-30

Family

ID=13325833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6678486A Pending JPS62222730A (en) 1986-03-25 1986-03-25 Data multiplexing transmitter

Country Status (1)

Country Link
JP (1) JPS62222730A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010010278A1 (en) * 2008-07-22 2010-01-28 Stmicroelectronics (Rousset) Sas Multichannel transmission on unifilar bus
JP2012205232A (en) * 2011-03-28 2012-10-22 Denso Corp Information transmission apparatus
US8943254B2 (en) 2010-11-15 2015-01-27 Stmicroelectronics (Rousset) Sas Conversion of a single-wire bus communication protocol

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504910A (en) * 1973-05-10 1975-01-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504910A (en) * 1973-05-10 1975-01-20

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010010278A1 (en) * 2008-07-22 2010-01-28 Stmicroelectronics (Rousset) Sas Multichannel transmission on unifilar bus
FR2934390A1 (en) * 2008-07-22 2010-01-29 St Microelectronics Rousset MULTICANAL TRANSMISSION ON A UNIFIL BUS
US8509318B2 (en) 2008-07-22 2013-08-13 Stmicroelectronics (Rousset) Sas Multiple-channel transmission over a single-wire bus
US8943254B2 (en) 2010-11-15 2015-01-27 Stmicroelectronics (Rousset) Sas Conversion of a single-wire bus communication protocol
JP2012205232A (en) * 2011-03-28 2012-10-22 Denso Corp Information transmission apparatus
US8873645B2 (en) 2011-03-28 2014-10-28 Denso Corporation Information transmission apparatus

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