SU1638730A1 - Device for digital message reproduction - Google Patents

Abstract

The invention relates to a technique of reproducing digital messages and can be used in channels for reproducing digital information, for example, as part of storage devices from a moving medium. The purpose of the invention is to increase the reliability of reproduction of information. A device for reproducing digital messages containing a voltage source, connected to the first input of a summing amplifier, the output of which is connected to the second input of a comparator, the first input of which is connected to the information input of the device, and the output to the input of the first decoder, the first and second outputs which are connected respectively to the information and marking inputs of the second decoder, a series-connected reversible counter, a register, and a digital-analogue converter are inputted, It is connected to the second input of the summing amplifier, the delay element whose input is connected to the comparator output, and the output to the summing input of the reversible counter, the subtractive input of which is connected to the output of the encoder, the input of which is connected to the information output of the device and the first output of the second decoder, the second output which is connected to the inverting input of the AND circuit, to the installation input of the reversible counter and to the output of the device decoding failure signal, and the third output is connected to the forward input of the AND circuit, you od which is connected to the control input of the register. 1 il. i (L S 05 oo oo

Description

The invention relates to a technique for reproducing digital messages and can be used in channels for reproducing digital information, for example, as part of storage devices with moving media.

The purpose of the invention is to increase the reliability of reproduction of information.

The drawing shows the electrical circuit diagram of a device for reproducing digital messages.

The device contains a source of reference voltage 1, summing amplifier 2, comparator 3, first 4 and second 5 decoders, delay element 6, element 7, encoder 8, reversible counter 9, register 10 and digital-to-analog converter 11. Source output A reference voltage 1 is connected to the first input of summing amplifier 2, the output of which is connected to the second input of comparator 3, the first input of which is connected to the information input of the device. The output of the comparator 3 is connected to the input of the first decoder 4, the first and second outputs of which are connected respectively to the information and marking inputs of the second decoder 5. The remote outputs of the reversible counter 9 are connected via register 10 to the bit inputs of the digital-to-analog converter 11, the output of which is is connected to the second input of the summing amplifier 2. The output of the comparator 3 is connected via the delay element b to the summing input of the reversing counter 9, the subtractive input of which is connected to the output of the encoder 8. The second decoder 5 has t In the Output, its first output is connected to the information output of the device and the input of the encoder. The second input is connected to the inverting input of the element I 7, the installation input of the reversible counter 9, and the output signal of the failure from decoding the device. The third output is connected to the direct input of the element And 7 whose output is connected to the control input of the register 10.

The device works as follows.

The device operates under conditions when a redundant correction block code is used when recording and reproducing information. The UBX binary information reproduced from the carrier and amplified is delivered to the first input of comparator 3, the second input of which receives the corrected reference level Uon ± UUQn from the output of summing amplifier 2, the inputs of which receive the signal of the reference level Uotl from the output of source 1 of the reference voltage and the correction signal of the reference level ± Uon from the outputs of the analog-to-analog converter 11. At the output of the comparator 3, a binary sequence of the redundant channel code is formed.

In a redundant channel code, for example a code (10.3), an eight-bit combination (byte), representing one character, is converted into a redundant code sequence consisting of ten bits, is recorded on or played back from the storage medium.

The binary sequence from the output of the comparator 3 is fed to the input of the first decoder 4, in which the serial code is converted into parallel, and the redundant code is converted into non-redundant (for example, ten-bit code into eight-bit) and some errors are detected in the symbol (erase ) which are fixed as erasers. If the erase signal is not present, then the first output of the first decoder 4 converts the converted code to the information input of the second decoder 5. When the first decoder 4 detects an erase, zero code elements are formed at its first output, and a second signal produces a marking signal at the second output the input of the second decoder 5. The second decoder 5 works with code blocks. After accumulating in it a code block whose combinations are elements of the final Galois field, encoded with a block code (I, K), for example, a Reed-Solomon code, the second decoder 5, on the basis of calculating and analyzing syndromes and taking into account marking signals, corrects in code block possible errors and erase and gives information to the output device.

In order to correct the error packets, the second decoder 5 can be constructed taking into account the application of various laws of moving code blocks.

If the multiplicity of errors and erasures is higher than the correcting capacity of the code, then the second decoder 5 generates a decoding failure signal, and the entire decoded block is skipped. By this, the proposed device favorably differs from the prototype, since detected but uncorrected errors are not transmitted to the output of the device. The remaining units of the device are used to form the correction signal of the reference level as follows.

From the output of comparator 3, the reproduced binary sequence of signals through delay element 6 is fed to the summing input of the reversible counter 9. Simultaneously from the output of the device, the corrected information is fed to the input of encoder 8, which converts the parallel non-redundant code to the serial redundant channel code (for example, eight times a thousand times).

The corrected binary sequence of signals from the output of encoder 3 is fed to the subtractive input of the reversing counter 9.

The delay time Ј of the delay element 6 is chosen in such a way that the corrected binary sequence of signals at the output of encoder 3 corresponds to the time position of that binary sequence of signals that is obtained at the output of comparator 3, i.e.

Ј - Ј, + ZD, where 2, Јg. Ј, the delay times of signal processing, respectively, of the first decoder 4, the second decoder 5 and encoder 8.

After the processing of each code block is completed, the code DYH-Ng is recorded in the reversible counter 9, where Y is the number of ones in the binary sequence formed by comparator 3; H is the number of units in the binary sequence formed by the encoder 8. Thus, the D N code carries information about the reliability of the DBOCH sequence of signals generated by the comparator 3. If DK 0, then the indicated binary sequences are the same. In this case, we can assume that the comparator 3 operates in the mode when the level of the reference signal is located symmetrically with respect to the signal U & x. There is a reliable formation of a binary sequence comparator 3.

If or DC 0, then in the generated binary sequence of signals by the comparator 3 there occurs a predominant distortion of the formation, respectively, of units or zeros. In these cases, we can assume that the comparator 3 operates in the mode when the level of the reference signal is located asymmetrically relative to

signal UB) (which may be caused by the indicated factors. The reliability of the comparator 3 is reduced.

If the error rate does not exceed the correcting capacity of the code, then the second output of the second decoder 5 does not contain a decoding failure signal, and the signal with its

The third output, corresponding to the end of each code block, passes through the AND 7 circuit to the control input of register 10, rewriting the DN code from the reversible counter 9 into it and resetting the reversing counter 9 to the zero state (the reset circuit is not shown in the drawing). A reversible counter 9 is prepared for calculating the DY code for the next code block.

0 in accordance with the value and the sign of the code digital-to-analog converter 11 generates the corresponding reference correction signal

Level ± Dilp, which is summed

with Uor) and changes the conditions of operation of the comparator 3. There is an increase in the reliability of the formation of a binary sequence of signals by the comparator 3 due to the balancing of the level and the reference signal relative to the CHI-signal of UgX

If the error rate of the corrective capacity of the code, then the decoding failure signal from the second output of the second decoder prohibits the control signal from passing through the AND 7 circuit, preventing the census from register 10 of the next code N, and resets the reversible counter 9 to

0 zero state, preparing it for the calculation of the DN code for the next code block. In this case, the reference level is not corrected and retains its previous value,

5 Thus, the device establishes a feedback connection for the correction of the reference level of the comparator 3, which is associated with the correcting ability of the applied code.

0 By changing the parameters of the digital-analog converter 1 according to the experimental data in the device, it is possible to establish the optimal law of change of the signal value

In this device, the reliability of information reproduction is due to the balancing of the reference level of the comparator 3 with respect to UB) cy, and the symmetry breaking can be caused by the indicated factors.

The concept of symmetry needs to be understood in a wider sense than the simple relationship between UQrt and U6) l, since the device establishes through feedback the optimal symmetric reference level from the point of view of the reliability of reproduction of binary information.

The error rate of binary information playback in the symmetric channel is lower than in the unbalanced-1 nominal. The error rate when receiving discrete (binary) information is defined as

(4-.-K)

(one)

POY.2 f H1 - (

-W-fefl

(3)

+ e

Similarly, the probability of error is recorded when the threshold is shifted by 9.2 above the value 0.5, i.e.

f1 -PDO.Z-fo

(four)

Calculate the values of the probabilities of errors Rstsm, howl, Rosh 3 for two values of the parameters h, 3, Lg 4. The results of the calculations are summarized in table

+ e

-"(I

M2l

)}.

(2)

where h is the signal to interference ratio; (p () is the integral of the probability of GaueC

sa

This probability corresponds to the symmetric case, i.e. to the threshold level Chop wil) / 2, while the first summable term corresponds to the probability of an erroneous reception 1, and the second term corresponds to the probability of an erroneous reception 0.

The value of the parameter h in the playback systems must be equal to

h is 3-4. i

To compare the error probabilities for different threshold levels, formula (1) is brought to mind with an explicit value of the ratio of the threshold level to the signal. Then the formula (1) with Uon / Uex "0.5 takes the form:

 .5. # H) +

When the threshold is shifted relative to a value of 0.5, for example, 0.2 below, the threshold value for the selection unit is 0.7, and for the selection zero is 0.3.

In this case, the formula (2) takes the form:

five

0

five

0

five

The data in the table for the considered example shows that a violation of symmetry in one direction or another leads to a significant increase in the probability of binary reproduction errors with different signal-to-interference ratios.

The operation of the device is controlled by synchronization signals arriving at the clock inputs of the decoders and the encoder, i.e. the device uses reference clock signals (not shown in the drawing).

Claims (1)

Invention Formula A device for playing digital messages containing a register, a delay element, an encoder, a reference voltage source connected to the first input of a summing amplifier, the output of which is connected to the second comparator input, the first input of which is connected to the information input of the device, and the output to the input of the first decoder , the first and second outputs of which are associated respectively with informational and marking the inputs of the second decoder, characterized in that, in order to increase the reliability of information reproduction, an element I is inserted into it and a reversible counter connected via a register and a digital-to-voltage converter, the output of which is connected to the second input of a summing amplifier, while the comparator output is connected via a delay element to the summing input reversible counter, subtracting input . ± lyop connected to the output of the encoder, the input of which is connected to the information output of the device and the first output of the second decoder, the second output of which is connected to the inverting input of the element I, the set input of the reversing counter and the output bus of the decoding signal, and the third output connected to the forward input element And, the output of which is connected to the control input of the register. Vshh - Refusal to decode