SU1629987A1 - Pulse counter - Google Patents

Abstract

The invention relates to a pulse technique, and in particular to technical solutions of universal counting devices, the counting results of which can be read into an external device without interrupting the counting. The purpose of the invention is to expand the functionality by allowing the reading of correct information from the counter to an external device when the counting pulses are terminated, ensuring the generation of the counting result sign and presetting the sign by initial setting the device when the counter is reset. The device for counting pulses contains counter 1, display elements 3, element OR NOT 4. New in the device are a recording unit 5, a character unit 6, an indicator indicator 7, as well as the first 8 and second 9 registers, the corresponding outputs of which form the information output 10 devices. 5 il.

Description

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The invention relates to a pulse technique and can be used in automated systems for operational monitoring and control, where reversing the counting of pulses is necessary with the possibility of presetting the counter and reading the result of the counting into an external device.

The purpose of the invention is to expand the functionality by allowing the reading of correct information from the counter to an external device when the counting pulses are terminated, ensuring the generation of the sign of the counting result and presetting the sign, and also by the initial installation of the device when the counter is reset.

Figure 1 presents the block diagram of the pulse counting device; figure 2 - functional diagram of the recording unit; FIG. 3 is a functional block diagram of the sign; figure 4 is a functional diagram of the counter; in FIG. 3, temporary diagrams of modes of operation of the device as a whole.

A device for counting pulses (FIG. 1) contains counter 1, information outputs 2 of counter 1, indication elements 3, element OR NOT 4, record block 5, character block 6, indicator 7 signs, first 8 and second 9 registers, information output 10 devices, which are formed from the outputs of registers 8 and 9, which are connected in parallel, information inputs 11 of the first register 8, information inputs 12 and 13 of the second register 9, controlling output device 14, sign input 15 of the character block 6 together with information inputs of the counter 1 forms an information input 16 stroystva, the effluent input device 17, the first input of the recording device 18, the forward 19 and reverse 20 input counting device, the second recording input device 21, the first 22 and second 23 control inputs of the read device 24 records the output unit 5.

Information outputs 2 of the counter 1 are connected to the inputs of the display elements 3, the element OR NOT 4 and the registers 8 and 9. The input of the indicator 7 of the sign is connected to the output of the block 6 of the sign that is connected to the input of the register 9. The output of the element OR NOT 7 is connected to the first the input block is 6 characters and is up0

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ravl yushim entrance 14 devices. The first, second, third and fourth control inputs of the counter are connected respectively to the third, fourth, fifth, sixth inputs of the block of 6 characters, and are also connected respectively to the first, second, third, fourth inputs of the recording block 5 and form respectively the inputs 17-20 device, and the fifth control input of the counter 1 is connected to the fifth input of the recording unit 5 and forms the input 21 of the device. The sixth and seventh inputs of recording unit 5 are connected to the control inputs of the first 8 and second 9 registers and are inputs of 22 hours 23 devices, and the output of recording unit 5 is connected to recording inputs of registers 8 and 9.

Record block 5 (figure 2) contains three elements AND 25-27, three fortires 28-30 pulses, RS-flip-flop 31, P-flip-flop 32, element OR-NO 33 of the recording block, element AND-NOT 34, two elements OR 35 and 36 and the inverter 37. The inputs of the first element AND 25 are the third and fourth inputs of the recording unit, and the output of this element is connected to the inputs of the first 28 and second 29 pulse conditioners. The output of the first pulse shaper 28 is connected to the first input of the second element AND 26, the second input of which is connected to a test of the element OR-HE 33 of the recording unit. The first input of the element OR NOT 33 is connected to the inverted output of the RS flip-flop 31, the setup input of which is connected to the output of the third element AND 27, the first input of which is connected to the output of the second pulse former 29, and the second input of the element 27 is connected to the output of the inverter 37, which is connected to the fault input of the D-flip-flop 32. The input of the inverter 37 is the first input of the recording unit 5 The inverse output of the P-flip-flop 32 is connected to its information input, the direct output of the D-trigger 32 is connected to the second input of the OR-NOT element of the recording unit and clock in One D-flip-flop 32 is connected to the output of the NAND 34, the first input of which is connected to the output of the third pulse shaper 30, the input of which is the seventh input of the recording unit, and the second input of the NAND 34 is the sixth input of the recording unit. The first and second inputs of the first element OR 35 are respectively 15

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eye and fifth inputs of the recording unit, and the output of the first element OR 35 is connected to the first input of the second element OR 36, the second input and output of which are connected respectively to the output of the second element And 26 and the output 24 of the recording unit, which is connected to the reset input of the RS flip-flop 31.

The character block 6 (FIG. 3) contains six Q elements of the OR-NOT 38-43 sign block, two inverters 44 and 45, and an RS-tritger 46 sign block. The first inputs of the first 38 to the second 39 elements OR are NOT connected to the output of the first inverter 44, the input of which is the first input of the sign block, the second inputs of -gp of the OR-NO 38 and 39 are respectively the sixth and fifth inputs of this block , the first inverse inputs of the third 40 and fourth 41 elements OR are NOT connected and form the fourth input of the sign block. The second input of the third element OR NOT 40 is connected to the input of the second iverter 45, the input and output of which are connected respectively to the second input of the sign block and the second input of the fourth element OR-NOT 41, the output of which is connected to the first input of the fifth element OR-NOT 42, the output of which is connected to the setup input of the RS flip-flop 46, and the second input is connected to the output of the first element OR-NOT 38. The output of the second element OR-NOT 39 of the character block is connected to the first input of the sixth element OR-NOT 43, the output of which is connected to the reset input RS flip-flop 46, wto second input of the sixth OR-NO element 43 is connected to the output of the third OR-NO element 40.

The pulse counting device (Fig. 1) can perform the following functions: initial setting to the initial state, prerecorded information with a sign, continuous forward or reverse counting of pulses, reading the counting results without stopping the counting with the exception of information loss,

embraced them. In parallel, the waste pulse through the first input of the recording unit 5 is fed to the input of the inverter 37 (figure 2). The signal from the output of the inverter 37 is fed to the second input of the third element I 27 and from its output on the installation input of the RS flip-flop 3t sets a low voltage level at the inverse output Q of this flip-flop. The signal from the inverse output Q of the trigger 31 is fed to the first input of the element OR NOT. The signal from the output of the inverter 37 also enters the reset input R of the D-trnger 32 and sets at its direct output Q a low voltage level that arrives at the second input of the OR-NOT 33 element. As a result, the output of the OR-HE 33 element appears a high voltage level that goes to the second input of the second element AND 26. From the output of this element, the signal goes to the second input of the second element OR 36. So 25 as the OR 36 element is open with a low voltage level at its first input, then at its output a signal appears that resets the RS flip-flop 31p its reset input R. As a result, the inverse output Q of the RS flip-flop 31 shows a high voltage level and a low voltage level at the output of the OR-NO 33 element, which generates a low level at the second input of the And 26 element. Low level output element AND 26 is fed to the second input of the element OR 36 and at its output creates a low level, which is fed to the reset input R RS-. trigger 31 and sets a high level on the inverted output O of the RS trigger 31, which is the reason for the occurrence of a high 1 level on the output of the OR element 36, which is the output 24 of the recording unit 5. In this way, a recording pulse is formed at the output 24 of the recording unit 5 upon initial installation of the device. The initial setup signal also goes to the third input.

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if the last counting pulses came 50 blocks of 6 characters and transmitted to the third

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embraced them. In parallel, the waste pulse through the first input of the recording unit 5 is fed to the input of the inverter 37 (figure 2). The signal from the output of the inverter 37 is fed to the second input of the third element I 27 and from its output on the installation input of the RS flip-flop 3t sets a low voltage level at the inverse output Q of this flip-flop. The signal from the inverse output Q of the trigger 31 is fed to the first input of the element OR NOT. The signal from the output of the inverter 37 also enters the reset input R of the D-trnger 32 and sets at its direct output Q a low voltage level that arrives at the second input of the OR-NOT 33 element. As a result, the output of the OR-HE 33 element appears the high voltage level that goes to the second input of the second element AND 26. From the output of this element, the signal goes to the second input of the second element OR 36. Since 5 as the OR 36 element is opened by a low voltage at its first input, then its output is is a signal resetting the RS flip-flop 31 by its reset input R. As a result, the inverse output Q of the RS flip-flop 31 shows a high voltage level and a low voltage level at the output of the OR-NO 33 element, which generates a low level at the second input of the And 26 element. Low level output element AND 26 is fed to the second input element OR 36 and at its output creates a low level, which is fed to the reset input R RS-. trigger 31 and sets a high level on the inverted output O of the RS trigger 31, which is the reason for the occurrence of a high 1 level on the output of the OR element 36, which is the output 24 of the recording unit 5. Thus, a recording pulse is formed at the output 24 of the recording unit 5 during the initial installation of the device. The initial setup signal also goes to the third input.

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during the previous read operation.

The device is reset to its initial state by a positive impulse arriving at the fault input 17 of the device. According to FIG. 1, this pulse through the first control input of the counter enters the reset inputs of the counting decades 47-54 (FIG. 4) and

the input of the fourth element OR NOT 43 (fig.Z). The latter is opened by a low level at the first and second inputs, because it implies the absence of counting pulses +1 at the second input of the second element OR-NOT 39 and the presence of a high level of the WRf signal at the first input of the third element OR-NOT 40. Then the signal

the initial installation from the output of the element OR NOT 43 is fed to the reset input R of the RS flip-flop 46, it is set to a low level at its direct output Q, which is the output 13 of the 6-digit block. The low level at output 13 of the block of 6 characters corresponds to the plus sign.

Thus, the initial setting by the signal R on the device input 17 zeroes the counter 1, writes a plus sign in the block 6 characters, writes information from the output of the block 6 characters and from the information outputs 2 of the counter t into registers 8 and 9 with a signal from output 24 of the recording unit 5 (figure 5).

Pre-recording information into the device occurs in two cycles in the following sequence. In the first cycle, first the information input 16 of the device is fed to the first 16-bit word, which is then fed to the information inputs D of the counting decades 47-53 and to the inputs of the switch 55 (Fig. 4). After that, the second recording input 21 of the device is fed to the recording differential arriving at the fifth input of the counter 1. Through the inverter this differential enters the recording inputs of the counting decades 47-50 and captures the information present at the information inputs D. Parallel recording the differential with The second recording input 21 of the device enters the fifth input of the recording unit 5 and is transmitted to the second input of the first element OR 35. From the output of this element through the second element OR it enters the output 24 of the recording unit. In the second recording cycle, the second 16-bit word is first fed to the information input 16 of the device, and the third input of the sixth element OR-NO 43 is the third input of the character block, the output of which is the direct output of the trigger 46.

The counter 1 unit performs summation or subtraction of pulses arriving at the inputs 19 or 20 of the device. Information about the counting results is fed to information output 2 of counter 1. Display elements 3 convert the binary-decimal code present on information outputs 2 of the counter into visual information. Element OR NOT 4 monitors the status of information outlets.

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2 counters 1. When appearing on all outputs, 2 counters log. About the output of the element OR NOT 4 there is a signal log. 1, which through the control output 14 of the device can flow to an external device for direct control.

The recording unit 5, after each change in the state of the counter 1, generates at its output 24 a recording drop, by means of which the setting information on the information outputs 2 of the counter 1 is recorded in registers 8 and 9. This is achieved by recording all signals that can change the contents of counter 1. These are forward counting pulses +1 and counting pulses -1, respectively, fed to forward 19 and reverse 20 counting inputs of the device. These are the preliminary recording signals WRj and WR, arriving at the first 18 and second 21 recording inputs of the device, respectively, and a reset signal, arriving at the device fault input 17. Upon receipt of any of the listed signals, after the end of the input processes in the counter 1, the recording differential is generated at the output 24 of the recording unit 5, which then goes to the recording inputs of registers 8 and 9.

Upon the passage of counter 1 through zero and the presence of summing pulses of direct counting at the input 19 of the device, the block 6 of the sign at the output generates a low voltage level corresponding to the plus sign. If the counter goes through zero during the presence of the counting down counting pulses at the device input 20, the character block 6 generates a high voltage level at the output, corresponding to the minus sign (Fig. 5). During the recording of information into the reversible counter 1 by the WR signal at the device input 18, the sign unit generates a voltage level at the output corresponding to a plus or minus depending on the level present at the sign 15 of the sign block 6 according to the time diagrams (Fig. Ј). When the counter 1 is reset by the signal R at the device input 17, the sign unit 6 generates a voltage level at the output corresponding to the plus sign (Fig. 5). The output of sign unit 6 is provided to informational code 13 of register 9 and

this makes it possible to read the mark into an external device.

Indicator 7 characters converts the signal coming from the output of the block 6 characters into a graphical representation of the plus or minus signs. Registers 8 and 9 serve for simultaneous fixation of 30-bit information from the informational outputs 2 of counter 1 and the sign for the purpose of subsequent output to the 16-bit output 10 of the device. This is done by the read signals RD, and that are applied to the pack.

equal inputs 22, 23 of the device (Fig. 5). At the same time, in the fifteenth bit of the word there is information about the sign, which is fed to the second input 15 of the block 6 of the sign. Information from the information input 16 of the device is fed to the information inputs D of counting decades 47-53 and to the inputs of switch 55. After that, the first recording input 1.8 of the device is fed to the recording differential through the inverter fed to the recording inputs C of counting decades 51-53. Parallel recording differential arrives at the control input of the switch 55 and

connects the inputs of the latter to the information block of 6 characters. Counting pulses

tions of the counting decade. Recording differential from the first recording input 18 of the device is also fed to the second input of the recording unit 5 to the fourth input of the 6-character block. From the fourth input of block 6, the inverted recording differential WRf goes to the first inputs of the third 40 and fourth 41 elements OR-HK, depending on the signal level at the second input 15 of block 6, sets the RS flip-flop to the appropriate state (Fig.5). From the second input of the recording unit 5, the recording differential WRf goes to the first input of the first element OR 35, from whose output through the second element OR 36, enters the output 24 of the recording unit 5 and records the information present at the outputs 2 of the counter 1 and at the output of the block 6 . This pre-records the information into the device.

Forward and reverse counting of pulses is performed when pulses are received, respectively, at inputs 19 or 20 of the device. In this case, the pulses from the input 19 of the device arrive at the forward counting input of counter 1, which

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is a direct counting input +1 decade 47. In the direct counting process, decade 54 with the arrival of the fourth pulse at its input +1 at output Y4 generates a high level and, via the OR element, resets the decade to its original state. This ensures that the bits of the high decade 54 are up to three. This allows the bits to be reserved. When counting back from the device input 20, the pulses go to the counting return input of counter 1, which is the return -1 input of the counting decade 47. In the counting process, after zero In the state of decade 54, the first impulse arrives at its countdown input; at its outputs Y1 and Y8, high levels appear that generate a low level at the output of the NAND element. This level arrives at the input of Decade 54 through the AND element and records the high levels at two lower bits of the decade 54. This is because the switch 55 is in the state shown in Fig. 4. Counting pulses also go to the third and fourth inputs of recording unit 5 and to the fifth and sixth inputs.

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The entries that go to block 5 are collected by the first element 25 And. From the output of this element, the pulses generated by the counting pulses of forward or reverse counting are fed to the inputs of the formers 28 and 29 of the pulses. The first driver 28 extends short counting pulses, with a memory card (which, for a certain time, closes the second element I 26 at the first input), preventing the recording signal from being generated at inputs 1, 6, 7 of the recording unit 5. The second pulse driver 29 generates a short pulse from the back edge of the counting pulse. Thus, the required delay of the pulse at the first input of the third element And 27 relative to the leading edge of the counting pulse. The lower the pulse from the first input of the element And 27 is fed to the set input S of the RS flip-flop, low The second level from the inverse output Q of this trigger enters the first input of the OR-NK 33 element. The second input of the OR-NOT 33 element also has a low level, while the output of the OR-NOT 33 element appears a high level arriving at the second input the second element And 26. At the appearance of high 15

A high level appears at the output of the driver 28 at the output of the AND 26 element, which through the second input of the second element OR 36 enters the output 24 of the recording unit 5 and parallelly through the reset input D resets the RS flip-flop 31 to the initial state.

Thus, after each counting jg pulse, information about the state of the counter by means of a recording pulse from output 24 of recording unit 5 is recorded in registers 8 and 9. If a log is present on all outputs 2 of counter 1. Oh, then at the output of the element OR NO 4 there is a high level, with which you can directly control the external device. Moreover, at a high level at the output of the element OR NO 4, the first and second elements OR NOT HE 38, 39 of the block 6 of the character are open low level arriving at the first inputs of the elements OR-HE 38, 39 from the output of the first inverter 44. When the first direct counting pulse arrives at the fifth input 19 (FIG. 3) of the sign unit 6, the pulse through the second element OR NOT 39 and the first entry of the fourth element

OR NOT 43 is applied to the fault input R of the RS flip-flop 46 and sets at its forward output Q, which is the output of the 6-digit block, low level, 20

corresponding to the plus sign. This level arrives at the second information input 13 of the second register 9 and at the input of the indicator 1 character. If the countdown pulse first appears, it is fed from the sixth input 20 of the 6th character block to the second input of the first OR-NOT 38 element and from its output, through the second input of the fifth OR-NOT 42 element is transmitted to the installer.

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during the counter through zero, the sign signal at the output 13 of the block 6 of the sign is changed, and thus the sign can be indicated by the block 7.

The counting results are read using control signals supplied to the first 22 and second 23 control inputs of the device. The reading is performed in two cycles. In the first cycle, the first control input 22 of the device is given a RD-read signal in the form of a low level. From the first control input 22 of the device, the signal is fed to the sixth input of the recording unit 5 and to the control input of the first register 8. A low level at the input 7. The register 8 turns off the high impedance state at the output of the register and the information that is last recorded in the register recording impulse from the output 24 of the recording unit 5, enters the information output 10 of the device. At the same time, the recording signal RD is fed to the second input of the NAND 34 element of the recording unit. Then, the signal from the output of the IS-NE element 34 is fed to the input C of the D-flip-flop 32 and puts its direct output Q in a state with a high voltage level. It is assumed that D-flip-flop 32 was previously in the reset state. A high level from the Q output of the D-flip-flop 32 closes the OR-NOT 33 element and prohibits the generation of write pulses at the output 24 of the recording block 5. After reading the information from the information output 10 of the device, the low level signal RTlj from the output 22 is removed. But since D-flip-flop 32 remains in its previous state, counting pulses cannot generate pulses.

S input RS flip-flop 46 and set-45 records at the output 24 of block 5 records.

At the direct output O of the trigger, there is a high level corresponding to the minus sign, which arrives at the output of the 6-digit block. When the next counting pulse arrives, the “trigger 46” does not change, since the elements OR-NOT 38 and 39 are closed by a high level at the output of the inverter 44. At this input of the inverter, corresponding to the first input of the 6-character block, there is a low level from the output of the element OR -NON 4, which is due to the non-zero state of counter 1. Thus, during the counting process, when

During the second read cycle, a second read signal RD2 is supplied to the second read control input 23 of the device. This signal on the control input Z of the second register 9 turns off the high-resistance state at its output, and the information fixed in register 9 goes to the information output 10 of the device. Simultaneously from the seventh inlet and block 5 of the recording signal RD4 is fed to the input of the third driver 30 This driver generates a short output pulse only during the transition

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during the counter through zero, the sign signal at the output 13 of the block 6 of the sign is changed, and thus the sign can be indicated by the block 7.

The counting results are read using control signals applied to the first 22 and second 23 control inputs of the reading device. The reading is done in two cycles. In the first cycle, the first control input 22 of the device is given a RD-read signal in the form of a low level. From the first control input 22 of the device, the signal arrives at the sixth input of the recording unit 5 and to the control input of the first register 8. A low level at input 7. of the register 8 turns off the high impedance state at the register output and information fixed in the register by the last recording pulse from the output 24 block 5 records, enters the information output 10 of the device. At the same time, the recording signal RD is fed to the second input of the element AND-NOT 34 of the recording unit 5. Then, the signal from the output of the NAND 34 element is fed to the input C of the D flip-flop 32 and transfers its direct output Q to a state with a high voltage level. It is assumed that D-flip-flop 32 was previously in the reset state. A high level from the Q output of the D-flip-flop 32 closes the OR-NOT 33 element and prohibits the generation of write pulses at the output 24 of the recording block 5. After reading the information from the information output 10 of the device, the low level signal RTlj from the output 22 is removed. But since D-flip-flop 32 remains in its previous state, counting pulses cannot generate pulses.

45 records at the output 24 of the block 5 records.

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During the second read cycle, a low level read signal RD2 is supplied to the second read control input 23 of the device. This signal at the control input Z of the second register 9 turns off the high-impedance state at its output, and the information fixed in register 9 is fed to the information output 10 of the device. Simultaneously, from the seventh input of block 5 of recording, the signal RD4 is fed to the input of the third shaper 30. This shaper forms a short output pulse only during the transition

voltage at its input from low to high. Otherwise, a high voltage level is maintained at the output of the shaper. From this it follows that the appearance of a low level of the signal RD at the input of the driver does not cause a change in the high level at its output. After reading the information from the information output 10 of the device, the low level of the signal RD is removed. This causes the appearance of a short pulse at the output of the imaging unit 30, which from the first input of the AND-NE element 34 is transmitted to the C 1) -trigger counting input 32 and leaves a low-level appearance at the O 1) -trigger 32 output. at the second input of the element ШШ-ИЕЕ 33 and opens it. If at least one counting pulse arrives at the end of the read cycle at the forward counting input 19 or at the reverse counting input 20 of the device, it is stored in the RS flip-flop 3t as a low level at the inverse output Q. After removing the inhibitory high level from the second the input element OR-NOT 33, if from the inverted output O of the RS-flip-flop 31 to the first input of this element receives a low level, the output of the element OR-HE 33 is a high level through the second element AND 26 and through the second element OR 36, coming on the output 24 of block 5 record. In parallel, a high level from the output of the element OR 36 enters the reset input R of the RS flip-flop 31 and resets it. Thereafter, a high level disappears at the exit 24 of the recording unit 5 and the generation of the recording pulse ends. By memorizing the fact of the arrival of counting pulses by the RS-trigger 31, the recording unit 5 generates a recording pulse at its output 24 at the end of the second read cycle. This eliminates the loss of the last counting pulse when reading information into an external device, if this pulse came during the previous information reading procedure. This is represented by the timing diagrams in FIG. 5.

The use of the proposed pulse counting device is most effective in automated systems where the external control device is 0.

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The device only controls the process flow, and the control action, when it reaches a predetermined state, is generated by the device itself.

Claims (1)

Invention Formula A pulse counting device comprising a counter, the information outputs of which are connected to the inputs of the display elements, which are connected to the inputs of the OR-NOT element, characterized in that, in order to extend the functionality by enabling the information from the counter to be read into the external device and providing an indication the sign of the result of the account, as well as by the initial installation of the device when the counter is reset, a record block, a sign block, a sign indicator are connected to the output of the sign block, as well as the first and second registers, the corresponding outputs of which are connected in parallel and form the information output of the device, while the information inputs of the first register and the first information inputs of the second register are connected to the information outputs of the counter, and the second information input of the second register is connected to the output of the sign unit, the first input connected to the output of the element OR-NOT, which is the control output of the device, and the second input of the sign block with the information inputs of the counter forms the information The device's first input, the first, second, third, and fourth control inputs of the counter are connected to the third, fourth, fifth, sixth inputs of the character block, respectively, and also connected to the first, second, third, and fourth inputs of the recording unit, respectively, and form a reset the device input, the first recording input of the device, the forward and reverse counting inputs of the device, and the fifth control input of the counter is connected to the fifth input of the recording unit and forms the second recording input of the device, while the sixth and seventh input The recording unit codes are connected to the control inputs of the first and second registers and are the first and second control inputs of the reader, and the output of the recording unit is connected to recording inputs of the first and second registers, the recording unit contains three AND elements, three pulse makers, RS-flip-flop, U-term, OR-NOT element of the recording unit, AND-NEA element, two OR elements and one inverter, while the inputs of the first element Both are the third and fourth inputs of the recording unit, and the output of the first element I is connected to the inputs of the first and second pulse formers, the output of the first pulse generator is connected to the first input of the second element AND, the second input of which is connected to the output of the element OR NOT the recording unit and, the first input of which is connected to the inverse output of the RS flip-flop, the setup input of which is connected to the output of the third element And, the first input of which is connected to the output of the second pulse shaper, the second input connected to the reset input of the D-flip-flop, which is connected to the output of the inverter which is the first input of the block, while the inverse output of the D-flip-flop is connected to its information input, the direct output of the D-flip-flop is connected to the second input of the OR-NOT element of the recording unit, and its clock input is connected to the output of the the I-NOT unit whose first input is connected to the output of the third pulse generator, whose input is the seventh input of the recording unit, and the second input of the NAND element is the sixth input of the recording unit, the first and second inputs of the first OR element are respectively the second and the fifth inputs of the recording unit, and the output of the first element OR is connected to the first input of the second element OR, the output of the second element OR .plug to the reset R-input of the RS flip-flop and 27 o five 0 five 0 five 0 is the output of the block, and the second input of the second OR element is connected to the output of the second AND element, the sign block contains six OR-NOT elements, two inverters and an RS flip-flop, the first inputs of the first and second OR-NOT elements of the sign block are connected to the output The first inverter of the sign unit, whose input is the first input of the sign block, and the second inputs of the first and second elements of the OR-NOT sign block are respectively the sixth and fifth inputs of the sign block, the first inverse inputs of the third and fourth elements of the OR-NOT sign block together and forms the fourth input of the sign block, the second input of the third element OR-KE of the sign block is connected to the input of the second inverter of the sign block and is the second input of the sign block, and the output of the second inverter of the sign block is connected to the second input of the fourth element OR NOT of the sign block, the output of which is connected to the first input of the 5th OR element of the nak block, the output of which is connected to the setup input of the RS-flip-flop of the sign block, and the second input is connected to the output of the first OR-NOT block of the sign, the output of the second OR-NOT block sign Aka is connected to the first input of the sixth element OR NOT block of the sign, the output of which is connected to the reset input of the RS flip-flop of the sign block, the second input of the sixth element OR NOT of the sign block is connected to the output of the third element OR NOT of the sign block, and the third input of the sixth element The OR-NOT character block is the third input of the character block, the output of which is the direct output of the RS-trigger of the character block. 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