SU1617637A1 - Device for phase auto-tuning of frequency with synchronism indicator - Google Patents

Abstract

The invention relates to radio engineering. The aim of the invention is to expand the range of indication of synchronism. The device contains a first phase detector 1, a loop filter 2, a tunable generator 3, a second phase detector 4, a phase shifter 5, a first low pass filter 6, a threshold unit 7, an OR element 8, a weight adder 9, a second filter 10 and a threshold unit 11. C using a weight adder 9 of the output voltages of the first and second phase detectors 1 and 4, proportional to COSϕ (T) and SIN (ϕ (T) + Δϕ), produces a voltage proportional to SIN [ϕ (T) -45 °], without additional phase shifter and phase detector. With proper selection of the thresholds for blocks 7 and 11, the range of indication of synchronism significantly expands. 3 il.

Description

Sh

FIG. one

The invention relates to radio engineering and can be used in radio receivers, frequency synthesizers, and other devices where there are phase locked loops (PLLs).

The aim of the invention is to expand the range of indication of synchronism.

FIG. 1 shows a structural electrical circuit of a PLL device with synchronism indication; in fig. 2 is an example of the implementation of the principle electrical circuit of the weight adder; in fig. 3 — graphs of the voltages at the outputs of the second phase detector and the functional converter as a function of the phase shift.

The PLL with the si-chronism indication contains a perrzy phase detector 1, a petleg filter 2, a tunable oscillator 3, a second phase detector 4, a phase shifter 5, the first low pass filter b, threshold block 7, the OR element 8, the weight adder 9, the second filter 10 l additional threshold unit P.

Consider the operation of the device with the cosinusoidal characteristic of the first phase detector and the shear angle of the phases in the phase shifter equal to -45 °. This angle is optimal.

At the outputs of phase detectors 1 and 4, the voltage in any mode is determined by the phase difference f (1) between the 1-way reference signal and the oscillation present at the other input of the detector:

Ui.Kcos9 (t); U, KcosL (t) --- 45 ° j

 ) 4-45,

where K is the conversion factor of the phase detectors 1 and 4 (without limiting the common HJ H commonality

T-MOST).

Weight adder 9 is designed to provide a range of indication of capture from f-: 0 ° to and from the output voltages of the nair phase detectors 1 and 4 proportional to (() -45 j. In accordance with Fig. 2, the output voltage of the phase degenerator 1 with weight y is added to the output and voltage of the phase detector 4, i.e., the output voltage of the weight cyMNjaTopa 9

and 9 - - -v 2 Кс о S ф (i) 4 К S i fi I ф (t) + 4 5 ° | .

 K. cnsi9 (t) - l35 °.

Thus, due to the weight sum, the voltage is obtained with a phase shift of minus 135 ° with respect to U | without additional phase detector and Phase Bogo detector.

Constant components of stresses IJj. and Ua are allocated by filters 6 and 10 and supplied and the inputs of threshold blocks 7 and 1.1. In the synchronization mode, one of the threshold blocks 7 and 11 should not be removed from these constant components, which is achieved by the appropriate choice of their threshold values of apt and 7.i.

Usually, the constant components at the outputs of the phase detector 4 and the weight adder 9 are much smaller in the acquisition mode than in the tracking mode with the same values of φ (1), therefore the thresholds are determined by the requirements for providing the synchronization indication operating range . If the threshold blocks 7 and 11 in the entire range of initial frequency detunings corresponding to the capture band of the PLL do not work, then their outputs and, therefore, the output of the OR element 8 sets a logical zero voltage corresponding to the absence of synchronism.

After capturing, in synchronization mode, a phase shift between the reference signal and the output signal of the adjustable oscillator 3 is set in the PLL device, equal to ф and depending on the initial frequency detuning, and the voltage Ui, Uii and Ug are converted to:

i1so Xo5fgo ;,

SP "-Kzt (f" + 45 °);

()

The nature of these dependencies on (p is shown in FIG. 3.

With the cosine and triangular characteristics of the phase detector, the stability of the PLL system is provided only at the section of the characteristic of the first phase detector 1 from O to 180. Consequently, it should be within these limits when it is necessary to provide a reliable indication of synchronization. This entire range is covered by the operation of the second phase detector 4 and the weight adder 9 with the corresponding threshold blocks 7 and; if their threshold voltages are chosen to be (0.65-0.7) Umax.

In this case, the second phase detector 4 and the threshold unit 7 indicate synchronism at, and the weight adder 9 and the additional threshold unit II - at 180 °.

Consequently, in the entire zone of stable values of fso, one of the threshold blocks 7 n I 1 is triggered, at the outputs of which the voltage of a logical unit appears. This voltage passes to the output of the element OR 8, and; There is synchronism.

The operation of threshold blocks 7 and 11 outside the zone 0 ° f: 180 ° is not dangerous, since going out q;, / 3 beyond this gona means a loss of stability and an instantaneous transition of the F.LPCH device to the beat mode, and in the beat mode constant voltage U4 and Ug below the thresholds of the threshold blocks 7 and 11,

Claims (1)

Invention Formula A phase locked loop with synchronization indication, a tunable oscillator connected to the ring, a first phase detector, the other input of which is a reference signal input, and a loop filter, as well as a second phase detector connected in series, a low-pass filter and a threshold unit, the first input The second phase detector is connected to the input of the device, and its second input is connected to the output of the adjustable oscillator through a phase shifter, characterized in that, in order to expand the operating inUif of range synchronization synchronization, a weight adder, an additional low-pass filter, an additional threshold block and an OR element, whose other input is connected to the output of the threshold block, are connected to the outputs of the phase detectors, and the other input is connected to the output of the threshold block on the AF, where 90 °, and the threshold value Un of the threshold blocks is chosen from the conditions, respectively) {and (f) | r., where, P (f) is the characteristic of the phase AeTeKtopa. b ,, - Ui, Un7-Unll - (0,65-0.7) and nffKC f, 00