SU1608711A1 - Device for selecting images of objects - Google Patents

Abstract

The invention relates to automation and computing and can be used to determine image parameters in technical vision systems and image recognition devices. The purpose of the invention is to expand the field of application by making it possible to determine the connectivity of an object. The device contains a television sensor, a quantizing unit, a generator, an image number code generation unit, a code comparison unit, a reversible counter, two imagers, three delay elements, a trigger, three OR elements, two switches, a interface block, a registration unit, a comparison element and a selector. . 1 hp f-ly., 6 ill., 1 tab.

Description

The invention relates to automation and computing and can be used to determine the parameters of images in vision systems and in devices for image recognition.

and the spruce of the invention is the expansion of the area of wintering due to the provision of certainty and connectivity of the object.

Figure 1 presents the block diagram of the device; Fig. 2 shows the functional block diagram of the interface; in Fig. 3, it functions as an execution of the functional diagram of the selector; In Fig. 4, an example of the execution of the functional scheme of the registration block; Fig. 5 shows an example of the implementation of the functional diagram of the driver; Fig. 6 is a timing diagram explaining the main c / 1 of the operation of the device.

The device contains a television. sensor 1, quantization unit 2, 3 clock pulse generator, formation unit 4

Image number code, code comparison block 5, reversible counter 6, first 7 and second 8 drivers, first 9, second 10 and third 11 delay elements, ig igger 12, first 13, second 14 and third 15 OR elements, first 16 and second 17 switches, interface 18, registration 19, comparison element 20, selector 21, synchronization input 22, first 23, second 24 and third 25 outputs of the device.

Interface unit 18 (FIG. 2) contains the first 26 and second 27 memory elements, the adder 28, the first 29 and second 30 registers, the first 31 and second 32 switches, the comparison element 33, the counter 34, the HE element 35, the first 36 , second 37, third 38, fourth 39 and 40 elements OR, first 41, second 42, third 43, fourth 44, fifth 45, sixth 46 and seventh 47 delay elements, first 48, second 49 and third 50 elements AND , first 51, second 52, third 53 and fourth 54 decoders, ele

About About 00 VI

ment 55 stack memory, first 56 and second 57 groups of information inputs, first 58, second 59 and third 60 control inputs, clock 61 and synchronizing 62 inputs, first 63 and second 64 groups of outputs, first 65, second 66 and third 67 exits.

The selector 21 (fig.Z) contains the first 68 and second 69 decoders, the first 70 and second 71 elements And, the element 72 of the delay, the first 73 and second 74 inputs, a group of inputs 75, the first 76, the second 77 and the third 78 outputs and clock input 79.

The registration unit 19 (FIG. 4) contains the first 80, second 81, third 82 and fourth 83 counters, first 84 and second 85 elements AND, first 86 and second 87 elements OR, first 88 and second 89 delay elements, first 90, second 91, third 92 and fourth 93 inputs, clock 94 and synchronizing 95 inputs, first 96, second 97 and third 98 outputs.

The driver (figure 5) contains the decoder 99, the element 100 delay, the input 101, the clock input 102 and the output 103.

The timing diagram (Fig. 6) shows the pulses 104 at the output of the generator 3 and the pulses 105 of the synchronization of the television sensor 1 (where 1frame is the forward time of the image readout beam; to6p. The time of return of the readout beam of the image), the pulses 106 at the input 22 devices, pulses 107 at the output of the imaging unit 8, pulses 108 at the first input of the selector 21, pulses 109 at the output of the trigger 12, pulses 110 at the input of the trigger 12, pulses 111 at the fourth input and the third output of the registration block 19, pulses 112 at the clock input of the block 19 registration, momentum 113 at the synchronization input of the interface unit 18, pulses 114 at the third input and the first output of registration unit 19 (where m is the number of objects), pulses 115 at the second input and second output of block 19 (where K is the number of nodes) and pulses 116 at the first input of block 19 (where n is the number of links in the node).

The device works as follows.

An image representing arbitrary shapes is scanned by a television sensor 1 and quantized to two levels by a quantization unit 2. The binary video signal from the output of the quantization unit 2 is fed to the first input of the image number code generation unit 4. During frame reading, trigger 12 is in state O, and during reverse, in state 1.

In the process of reading the image, the number of the initial element of the object is entered into the first memory element 26 of the interface block. At the same time, at the third output of block 4 of the formation of the code of the image number, an impulse appears, the duration equal to the time of decomposition of one element in the line, and through the element 10 the delays and the elements OR 14 and 13 enter the second

0 control inputs of the first (address) 16 and second (information) 17 switches and to the second input of the interface unit 18, where through the first element OR 36 is the input Record of the first memory element 26. The information about the object number from the first output of the image number code generation unit 4 is switched through the second groups of information inputs of the switches 16 and 17 and is recorded in the first memory element 26. In the case of intersection of areas belonging to the same object with different initial numbers, a pulse arises at the output of the code comparison unit 5, which through the first generator 7 enters the first input of the conjugation unit 18. This signal by means of the first delay element 41, the third element OR 38, the first element AND 48, the first register 29, the adder 28, the fourth delay element 44 and the second element OR 37 increases the code of the second memory element 27 by one and the lower bits of the address of the second memory element 27 through the first switch 31 have an adder code 28. Due to the delay of the signal from the output of the image number code generation unit 4 on the first delay element 9 to the memory unit 26 of the mating unit 18 at the address

0 determined by the code of the first output of the image number code generation unit 4 is recorded with the information code from the second output of the image number code generation unit 4, and through the clock into the first

5 memory element 26 at the address determined by the code from the second output of the image number code generation unit 4, records information determined by the code from the first output of unit 4. As a result, at each address determined by the code on the first group of information inputs of the unit 18, in the first memory element 26, a communication is recorded, and in the second memory element 27, the number

5 links of the node with the given number.

After reading the image frame, a pulse is applied to the clock input of the imager 7, which transfers trigger 12 to state 1. The pulse from the output of block 8 sets the counters to input e, the third slider trigger 33, to the initial state

of this

g

ten

15

b | 1 19 registration via clock unit. The same pulse through the element OR 15 is applied to the sync input of the interface 18 and the circuit consisting of elements 1, 42.51, 43.39, 49.53, 52.54, 30, 40, from the output of trigger 12 commutes ; commutator 17 N-bit output counter 6, in which the code of the maximum element recorded on the second group of information 18 interfaces is recorded to this, and through the commu- nication - the first group (N bits) of the output 18 interface marry his first information entry. The main mode is to process the accumulated memory and transfer it through the block: to the outputs of the device. The scheme functions as follows. A 20-e pulse from the synchronization block 18 mating is fed to the input of the fifth element OR 40 and the first input input of the switch 32, which is a copy of the object recorded in the register- hioMepa register 5 and 40 the even-J9 elements OR and the second element are fed to the counting input 34 and changes its code by one; it is compared in the element 33 with the comparison of the second memory element 27 is written off in turn from the exponent 28. The result of the comparison is the second input is greater than the first output from the output of the comparison element with the delay For one clock on the element 42, delays and pulses from the fourth element OR 39 are also received by one clock to the input of the decoder 51, which operates in the co-table of states, the case on the first output of the de-51 1 passes From the first memory element 26, the storage stack element 55 of the memory and the clock pulse is modified 4. This process takes place until those of the first memory element 26 fail to store all private connections, the number 4x is stored in the second element 27 After the selection of private connection of the pro-code} of the counter and the code of the second element 27 of the memory, while During the decoder 51 which is on resets the counter 34 and state, sets the first 9 in the null state, or ent through the secondary 37 writes the second memory 7, the source code is zero, and

31.34,

32.55.

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the second; exit with zader; | whoa

In this coder, the N-bit forma

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In the first memory element 26, through the first element OR 36, the counter code 6 is written. The code of the item currently being viewed. This signal is used to highlight the following links, if the code on the N-bit output of the stack memory element is not zero, as evidenced by the zero level at the output of the fourth decoder 54, then a pulse appears at the second output of the third decoder 52, which, with a delay of one clock cycle in delay element 47, rewrites the N-bit code from the output of element 55 through the second switch 32 into the second register 30 and with a delay of one cycle at the sixth delay element 46 shifts the information of element 55 in about atnom direction by one step,

With the appearance of the signal at the output of the fifth element OR 40, the process of selecting communications at the new address is repeated until all communications have been completely reviewed. If the code at the output of the element 55 is zero, a pulse appears at the first output of the third decoder 52, which is the first output of the conjugation unit 18. During this cycle, when each connection is fixed (repetition 1 at the first output of the third state decoder), a pulse appears at the second output of mating unit 18, and when all links in the node are searched, at the third output of mating unit 18.

The pulse from the first output of the interface unit 18 through the third delay element 11 reduces the state of the counter 6 by one. The same pulse through the first input of the selector 21, the second element And 69 of the selector 21, the element 72 of the delay of the selector 21 and the third element OR 15 enters the synchronizing the input of the mating unit 18 and starts it again, but now an object is considered, whose number is one less than the previous one.

In case all objects are viewed, counter code 6 takes state 1. This state is fixed by the second decoder 69 of selector 21 and permits the passage of a pulse from the first input of the selector through element I 68 to the first output of the selector 21. On this pulse trigger 12 goes to state O, counter 6 and block 4 of forming the code of the image number are transferred to state O and through block 19 of registering the pulse of the first output of the selector enters the output of the device. After this, the cycle of operation is repeated. During the return stroke, the number of connections in the node is recorded in the counter 83 of the registration unit 19, the number of connections in the object is recorded in the counter 80, the number of nodes in the counter 81, and the number of objects in the counter 82. In the process of work in the counters - the number of nodes, communication and object under consideration. Information about the last object considered is saved until the end of the next frame,

The imager (FIG. 5) selects the leading edge of the pulse, the decoder 99 gives output 1 only in case 1 at the first input and O at the second input, in which is the input signal delayed by one clock cycle.

Thus, when building a readout and forming a binary image with elements aij, where 1 is the current element number in the line, J is the current line number, the next number is assigned to the image element of the object, i.e.

Ni, j, L NL-I X aij, (1)

where ai 1, if the element is dark, aij O, if the element is light, if

N (i - 1) j P Ni (j - 1) O (2)

regardless of L,

where L is the current image number of the object;

The associated pixels are labeled with the same number, corresponding to the conventional image number of the object as a result of deciding the following recurrence relation:

NIJ.L N o - i), j, L and N i. O - i) .L X Qi.j X

xai.j and A (n-Hj), (M) LXb (i-j) j (3)

where Ai, j, L Ni.j.L X (5 ij, (4)

a, .. jn a (i-i) (j + i) (5)

bi, j aij n ai -i, j (6)

where d is the difference of the indices I in the values of bij on the 0 + 1) th and J – M counts, which follows from the continuity condition, which means that with the existence of (5), i.e. (5ij 1, necessarily exists (6). Relations (4) and (5) are fulfilled only for image elements with a negative slope. From relation (3) it also follows that in the case of the inequality L and L, the intersection of In order to eliminate the heterogeneity of the marking, the preceding elements are assigned a single number and fix the intersection area of the elements with different numbers, but

Qil 1, (7)

if a

N 1-J.L O, N I, j -1, L 5 O;

(eight)

N i-i.j, L N i, j-i.L

belonging to the same object.

In the process of reading the image, the numbers of the initial elements of the object are remembered; when conditions (1) and (2) are fulfilled, and the beginning of the intersection areas:

Zi, j Qi.n 6 (i-i), j

After reading the image frame, for example, during the reverse sweep stroke, the same areas are assigned to all related areas of the same object.

the number, simultaneously for each object, is calculated the number of links, the number of links in each node of the object, the number of nodes of the object, and the number of all objects in the image.

The proposed device allows to expand its area of application due to the possibility of selectively characterizing parameters such as the connectivity of an object, the number of nodes, the number of links for each node and for the object as a whole,

Claims (2)

Claims 1. Device for the selection of images of objects containing television a sensor connected to a quantization unit, the output of which is connected to the first input of the image number code generation unit, the first and second outputs of which are connected respectively to the first and second inputs of the code comparison unit, the output of which is connected to the second input of the image number code generation unit, the third output connected to the summing input of the reversible counter, output a clock generator is connected to the third input of an image number code generation unit, characterized in that, in order to expand the field of application by providing a definition of connectivity object, the first and second switches, a conjugation block, a selector, a registration block, a comparison element, the first, second and third delay elements, the first, second and third elements OR, the trigger, the first and second drivers, the input of the first driver is connected to the output of the code comparison unit, and the output is connected to the first input of the interface unit, the first control input of the first switch, the first input of the first OR element and the input of the first delay element, the output of which is connected to the first the input of the second element or the first control input of the second switch, the second corner by the way NA mates are keys LCDs from 51 measure le torus mutator first us of wts AOE1 XOjEl KG bls CIS Gro fine Bbii pefym I ale yen sch swarm out mates by pen tion under the second whom him not mates pulses Pervego handles tion org Era LI ten the main input of which is connected to BE 1 of the first element OR, the second input is connected to the output of the second delay 1, the input of which is connected to the third output of the image code forming unit, the second inputs of the un-block and the second element OR to the output of the second element of the delay, the group of outputs of the reversible counter is united with the first groups of inputs CE-e. the comparison element and the second com-, second and third groups of inputs I and the second switch are connected respectively to the first and second outputs of the block forming the number 15 code number, the second control input of the switch is connected to the output of the p OR element OR, the first group I-to the first group of information you-. of the interface unit, and the group of outputs is the 20th group of information inputs: interfaces, the second group of informational inputs of which is connected to 1pe of the outputs of the second switch, the first output of the interface unit is connected to 25 mm of the selector and the input of the third cop delays, the output of which is connected to the subtracting input of the reversing hick, the second group of information outputs of the interface block is connected to the second a group of inputs of the comparison element:) whose D is connected to the second input of the selector, the second and third outputs of the block | respectively, the third and fourth inputs of which are connected to the second inputs of the register block, 35, | {: corresponding to the first and outputs of the selector, the third output). connected to the first input of the third OR; the output of which connects to the synchronizing input of the block, the output of the clock generator is connected to the clock input of the first and second drivers, -o, the second and third elements of the 1, match block, register block - and the selector, the output of the second encoder is connected to the S-input with a trigger-second input of the third element and the synchronization input of the registration unit 50, the second output of the selector is connected with the R input of the trigger and the installation moves of the reversible counter and the air conditioner code block of the image number, the trigger trigger is connected to the third control inputs of the first and second commutators and interface block, the input The second actuator is synchronized with the device, and the first, second and 45 in the d go pack e ne w suns eta ten 15 20 5 0 five the third outputs of the registration unit are the corresponding outputs of the device, 2. The device according to claim 1, which differs from the fact that the interface block contains the element NOT, from the first to the fifth elements OR, from the first to the seventh delay elements, the first, second and third elements AND, the comparison element, the counter, the first and second switches, the first and second memory elements, the adder, the first and second register the first, second, third and fourth decoders and the stack memory element, the first group of address inputs of the first memory element is connected to the group of address inputs of the second memory element and is the first group of information logs one unit, the second group of address inputs of the first memory element is connected to the output of the first switch, the first control input of which is connected to the output of the first element NOT, and the second control input is the third control input of the block and connected to the input of the first element NO, first and the second group of information inputs of the first switch are connected respectively to the first and second groups of information inputs of the first comparison element and connected respectively to the output groups of the adder and counter, counting and y The setting inputs of which are connected respectively to the output of the second element AND and the second output of the first decoder, the first inputs of the first and second elements OR are connected to the first control input of the first register and connected to the output of the third element AND, the first input of which is combined with the first input of the third decoder and connected to the second output of the second decoder, the second input of the first element OR and the second control input of the first register are connected to the output of the first element AND, the third input of the first element OR is the second control input of the block, and the output of the first OR element is connected to the recording input of the first memory element whose output is connected to the information input of the stack memory element and is the second group of information outputs of the block, the input of the first delay element is combined with the first input of the third OR element and is the first control input of the block, the output of the third element OR is connected to the first input of the first element AND and the last bit of the second group of information inputs of the adder, the first group of information strokes which is connected to the output of memory element Etorogo group informa- n inputs of which is connected to the ionic the group of outputs of the first register, the group of information inputs of which is combined with the group of information inputs of the second decoder and connected to the group of outputs of the adder, the group of information inputs of the first memory element is connected to the second group of information inputs of the second switch and the second group of information inputs of the block the input of the second element I is connected to the synchronizing inputs of the first, second, third, fifth, sixth, seventh delay elements, the stack memory element, the second input the first element AND is the clock input of the block, the recording input of the second memory element is connected to the output of the second element OR, the second input of which is connected to the output of the fourth delay element whose input is connected to the output of the first element AND, the output of the first delay element is connected to the second the input of the third element OR, the input of the third delay element is connected to the output of the fourth element OR and the first input of the second element AND, the output of the third delay element is connected to the second input of the first decoder, the first input is orogo connected to the output of the second delay element having an input coupled to the output of the first comparison element Neny, the second output of the first decoder is connected to a first input of the fourth OR gate, a first control input the stack element of the memory is the second output of the blocks, the first input of the fifth element OR is connected to the first control input of the second switch and is the synchronization input of the block, the second input of the fifth element OR is combined with the second control input of the second switch and the input of the sixth element delay and connected to the output of the seventh delay element, the input of which is connected to the second output of the third decoder, the second information input of which is connected to the output of the fourth decoder, a group of inputs of which It is not connected with the first group of information inputs of the second switch and is connected to the group of outputs of the stack memory element, the group of outputs of the second switch is connected to the group of information inputs of the second register, the control input of which is connected to the first input of the fourth element OR and connected to the output of the fifth element OR, the output of the second decoder is connected to the input of the fifth delay element, the output of which is connected to the second input of the third element AND, the first output of the third decoder is the first output of the block, the output the second decoder is the second output of the block, the output of the third element is the third output of the block, the group of outputs of the second register is the first group of information outputs of the block.  23 7 g 25 -IS 65 75 o74 cz; FIG. 76 YU 77 I p 7J 7ffb FChZ and 9ff FIG. five