SU1606996A1 - Method and apparatus for multiple-track digital magnetic recording - Google Patents

Abstract

The invention relates to instrumentation, in particular, to recording and reproducing digital information on a moving magnetic medium, and can be used in digital multi-track tape drives. The goal is to provide the possibility of recording and reproducing information by arrays containing up to several tens of bytes, with monitoring the quality of the information and correcting it during playback and eliminating the effect of inter-track mismatches. The possibility of operating with small amounts of information is achieved by the fact that the flow of the recorded information in the recording process is divided into small quanta, which form the recording format. In an example of a specific implementation, the recording format contains 10 bytes of source information. The use of an iterative control code tied to the transcoding information recording format and a control code tied to the initial presentation of information allows for effective multi-stage quality control of the reproduced information, as well as the correction of single errors within the format. 2 sec. and 2 z. p. f-ly, 5 ill.

Description

The invention relates to instrumentation, in particular, to recording digital information on a moving magnetic medium, and can be used on digital multi-track tape drives.

The aim of the invention is to expand the recording of information by arrays containing up to several tens.

bytes, in quality control, information and its correction.

Figure 1 is a diagram of the formation of a signal structure on a tape; 2 is a functional diagram of a recording device; in fig. 3 - functional diagram of the code converter; FIG. 4 is a functional diagram of a write signal generator, variant 1; figure 5 - the same option 2nd.

A device for recording digital information (FIG. 2) contains a source of 1 information and control signals, with its first (infirmation) and second (synchronization) outputs. Connected to the corresponding inputs of the converter 2. codes, the third output with the input signal of the buffer orthogonal block (BOZU) 3 memory, the fourth output with the combined inputs of the 4. Read address counter and the BOSE reading signal input: 3. The 4-address counter with its outputs | 1 is connected in parallel to the inputs of the read address of the BOSE 3 and the 2-code converter, three groups of outputs of which are connected respectively to the group of information inputs of the BOSU, a group of inputs of the write address. BOSU and in parallel with the group of information outputs BOSU with the inputs of formers 5. recording signals The corresponding amplifiers of 6 recording signals and a block in series with them are connected to the outputs of the T. 5 telecommunication signals: 7 magnetic heads.

The code converter 2, whose circuit is shown in FIG. 3, in the recorder contains a counter 8 with a counting trigger 9 connected in series with it, a delay element 10 whose output is connected to the input of the counter 8, and the input combined with the input of the block 15 is constant the memory is the clock input of the converter 2j, the first inputs of the first) of the 8th group of 11 elements I, connected in parallel to the inputs of the first decoder 12, are connected to the inputs of the counter 8, which together with the output of the counting trigger 9, exits preo verters 2 codes. The outputs of the first decoder 12 are connected to the abrasive inputs of the multi selector 13, the two groups of inputs of which are connected respectively to the first group of inputs of the converter 2 codes and the outputs of the first register 14. counting flip-flops.- The outputs of the 1st 13 are connected to the address inputs of the fixed memory unit 15 The outputs of which are divided into two groups, one of which, together with the outputs of the first group of 11 elements, is And is connected to the inputs of the first register of counting triggers, and one of the outputs

Q 5 0 5

0 -. with

five

five

Dov is additionally connected to the second inputs of the first group of 11 elements I. The second group of outputs, connected to the inputs of the second register 16 of the counting flip-flops, is the second group of outputs of the 2-code converter. The outputs of the second register 16 of the counting triggers are connected in series with the static register 17 and the second group 18 of elements AND, the outputs of which are the third group of outputs of the converter 2 codes. The second group of inputs of the converter 2 codes is connected to the inputs of the second decoder 19, the output of which is connected to the control inputs of the second group 18 ajjementov I.

A shaper of a recording signal in the form of rectangular pulses, the functional diagram of which is shown in FIG. 4, contains a shift register 20 in the recording device, whose inputs are clock and information inputs of shaper 5, with the clock input also connected to the input of the first delay element 21, its output connected to the first input of the first element AND 22. The second input of the first element AND 22 is connected to the output of the last digit of the shift register 20, the remaining bits of which are connected to the input addresses of the block 23 PICs constant memory. The outputs of the fixed memory unit 23 are connected via a serially connected static register 24 to the parallel recording inputs of the initial state of the counter 25, the outputs of which are connected to the inputs of the OR 26 element. The output of the first element And 22 is connected to the parallel recording control input of the counter 25 and the second input The delay element 27, to the output of which the read control input of the storage unit 23 is connected. The sync frequency input of the driver is connected to the first input of the second element 28, the second input of which is connected to the output of the element OR 26, and the output to the counting input of the counter 25, its output connected to the input of the count Trigger 29. The output of the counting trigger 29 is output formulated. l 5 signal zapiski.

Boron the worldviewer 5 of the recording signal as a sawtooth signal, the functional diagram of which is shown in FIG. 5, shift register

thirty,. the first input of which is the information input of the imaging unit 5, the clock input of which is connected to the combined inputs of the three dividers of the clock frequency 31, 3233 and one of the inputs of one of the AND (second circuit) ZY-OR 34 elements. oh of the remaining two circuits And (first and third of the circuit) are connected respectively to the outputs of the first and second dividers 31 and 32 clock frequency, and the third divider 33 clock frequency is connected to the clock input of the shift register 30 and through the delay element 35 with the first inputs of the first 36 and wto 37 elements I. The second inputs of the And 36 and 37 elements are connected respectively to the outputs of the first and second bits of the shift register 30 and the combined third inputs are connected to the output of the third bit of the shift register 30. The outputs of the And 36 and 37 elements are connected to the installation inputs of the corresponding named after two triggers 38 and 39, the reset inputs of which, combined with the input of the counting trigger 40, are connected to the output of the counter 41. The first outputs of the triggers 38 and 39 are connected to the second inputs of the first and second circuits of the ZI-OR element 34, and the second outputs of the trigger 38 and 39 connect They are connected to two corresponding inputs of the third circuit AND element ZI-OR 34. The output of element ZI-OR 34 is connected to the input of the counter 41, the outputs of which are connected to the corresponding inputs of the binary-to-voltage converter, the auxiliary input of which is connected to the output of the counting trigger 40 and the output is the output of the former 5.

In General terms, the algorithm of operation of the recording device, a functional diagram of which is shown in figure 2, can be represented as follows.

The work cycle starts with the device setting to the initial state. Then, from the source 1 of information and synchronization signals, the input into the converter 2 of the code begins to receive information in the form of a sequence of bytes. Each received byte of information in code converter 2 is converted into the corresponding codes of the recording signal, and at the same time the control byte is being generated.

069966

code and parity codes of magnetic recording lines. The write signal codes are immediately transmitted to BOSE 3 in the form of a word connecting the recoded byte of information and the parity codes of the recoded byte in a format containing code units in bits 0, 10, and 13, bits 1 to 9 in bits code of recoded byte, in 11- and 12-bit bits parity codes for the previous even and odd bits and zero symbols in the last 14 and 15 bits. To form parity codes of 15 lines of magnetic recording, the write signal codes (only information codes and parity codes) are subjected to bitwise mod 2 modulation.

The control code also accumulates 20 by a bitwise sum modulo 2 of its intermediate values. The intermediate code control byte contains a parity code of the converted information byte, 25 four bits of the byte sequence number (only for bytes with an odd number of ones) and three bits of the specific code determined by the content of the encoded byte in accordance with the matrix coding 01010101 А- О О 1 1 О О 1 1

00001111, Recoding is performed by polling the ROM 15 in the code 2 converter at the address corresponding to the numeric value of the encoded byte. In zero-format format, the parity code of the byte content of the other encoded information is placed. In the 1-3rd bits, a specific part of the intermediate value of the control code is placed, in the 4th and 5th bits, the parity codes are placed to transcode the byte into even and odd bits, respectively. In the remaining bits (6-15), a write signal code, and in the 15th bit a code unit is always recorded.

The storage option of the ROM (octal representation) for the example in question is shown in Table 1.

After all the bytes included in the recording format are received and re-encoded, 5 encoding is performed in the recording code of the control code value accumulated by that time.

As a result, in BOSA 3 a region is formed, which is a code

1160

the display of the recording format, and on a separate register 17 in the converter 2 of the code - the word corresponding to the parity of the recording lines on the magnetic tape. This completes the cycle of the code converter, and the next cycle may be started.

In the new work, completely repeating the foregoing, recoding, a bath of information also arrives at WOW 3, however, is recorded in the adjacent section of the memory.

At the same time, reading begins.

information from the memory area filled in the previous loop. Moreover, if the recording was carried out along the lines of memory corresponding to the working tracks, then the reading is performed according to the columns of the memory corresponding to the sequence of measures (rows) of the magnetic recording. Thus, information will be transported and, as a result, a single input information stream at the input of code converter 2 is divided into a number of individual streams at the output of BOSC 3 by the number of working tracks. A reading of the parity code is applied to the reading cycle from BOSCU 3 magnetic recording lines from a separate register 17, in the converter 2 codes.

The next stage of transformations is the formation of a recording signal. The device in question offers two options for generating a recording signal, each of which is aimed at increasing the longitudinal recording density. In one case, when the recording signal is represented as a telegraph signal, additional phase modulation is performed, allowing a certain degree of reduction of phase distortion in the reproduced signal. In another case, the recording signal is formed by an E-shaped sawtooth signal having a substantially smaller width of the spectrum.

In the first case (the functional layout of the write driver is shown in FIG. 4) the code signal is fed to the shift register 20, and every time, as soon as the code unit is in the high bit of this register, the persistent memory unit 23 is accessed, in which

0

0

0

five

five

five

0

five

0

five

the numbers corresponding to the values of the additional delays are stored, inputted 1.x into the write signal phase.

In the second case (the functional diagram of the write signal generator is shown in Fig. 5), the code signal is fed to the shift register 30, and as a result of a logical analysis of the interval between the closest units to the input of the counter 41, the clock frequency is reduced, either directly or reduced in 2 or 3 times. As a result, a sawtooth voltage is generated at the output of the digital-to-voltage converter.

The generated signal is amplified and fed to recording magnetic heads.

The operation of the transducer 2 of the code in the device for recording performed in accordance with the functional circuit shown in FIG. 3 is as follows.

By the time the next byte of information arrives, a corresponding digital code is present on the 8 byte counter, under the effect of which a signal allowing the byte of information from the first inputs of the converter to pass through the multi selector 13 to the address inputs of the fixed memory unit 15 passes through the byte of information from the first byte of the converter from the group of elements And 11, and the output signal of the converter is a code signal that forms the address of the record of BOSU.

With the arrival of the next byte of information on the synchronization signal accompanying this byte, the ROM is polled to the address corresponding to the digital value of the received byte. The read code is distributed to converter elements as follows.

The parity code of the received byte of information arrives at the second inputs of the AND 1V elements and at the input. Of the first register bit of 14 counting triggers.

The control byte code (3 bits) is fed to the inputs of the 6th, 7th, and 8th bits of the register of 14 counting triggers.

Parity codes (2 bits) and information (9 bits) inputs the second register of 16 counting flip-flops and, accompanied by a code unit (15th format bit), to the first information outputs of the converter. Simultaneously on parity signal in co9

In accordance with the switched on set of elements AND 11, the code of the sequence frequency of the intermediate value of the control code arrives at the input of the 2–5th bits of the first register 14 of the counting flip-flops.

At the conclusion of the cycle of operation of the converter 2 of the code, the pulse of the synchronous code unit (the signal of the type - BBFiM), performed according to the scheme in FIG., Works as follows.

An information code, accompanied by a synchronization pulse, is fed to the input of the block and is recorded on the shift register 20. The output is older than the th digit of the shift register 20

The delayed element, 10 delayed-JQ, is connected to one of the inputs of the elekka, is fed to the input of the counter 8 and translates it into the next state.

After the last byte of information, which enters the recording format, passes the output of the decoder 12, a signal appears that switches the multi-detector to a connection to the address inputs of the ROM 15 signals from the outputs of the first register 14 of the counting flip-flops. Now, by the synchronization signal received at the input of the code converter, the byte of the control code generated on the register 14 of the counting triggers is converted into the code of the recording signal, and by the delayed signal the counter of 8 bytes goes to the initial state, and the overflow signal from its output switches the counting flip-flop 9. As a result, at the output of the write addresses in the WHICH code converter, the addresses corresponding to the new BOSC area are generated. In addition, by the overflow signal of the counter 8, the code formed on the second register 16 of the counting flip-flops is transmitted to the static register 17, and the register 16 is zeroed.

Reading the code from register 17 occurs through the second group of elements AND

18to the signal generated by the decoder 19. The read signal by the decoder

19 is formed by decrypting the code of the reading address from the BOSU corresponding to the reading address of the information of the fifteenth line of writing on the magnetic tape.

BOSU is built on register elements organized structurally in the form of a matrix. With this reading and. Records can be made both in rows and in columns of this matrix. In the device, the write to the BOSU is performed in rows, and the reading is done in columns. As an element base, elements of the orthogonal memory of the 537 RUD series can be used.

Signal conditioning unit in the form of a signal with rectangular differences 15

20

25

thirty

.35

40

45

50

55

And 22, the second input of which receives a synchronization pulse delayed in time on the delay element 21. If a code unit is recorded at this moment in the higher order of the shift register 20, the delayed synchronization pulse, passed through the AND 22 element, is fed to the input of the second delay element 27 and to the input of the pair-allelic code writing to the counter 25. Under the action of this digital signal the code from the static register is rewritten to the counter 25. As a result, the first input of the element And 28 gives rise to the enabling signal, which is valid until the counter 25 has states other than zero (the element OR 26 provides the transmission of signal as long as at least while one of the bits of the counter 25 will be written to the coded unit). Now, the input of the counter 25 receives the synchronization frequency from the input of the block, the transfer of the counter into a sequence of successive states. As soon as the counter finishes the counting cycle, an overflow signal is generated at its output, and the decisive signal disappears at the output of the AND 28 element. The overflow signal switches the state of trigger 29, providing a recording signal with a compensating additional phase modulation.

In parallel with this, a synchronization pulse, having passed through the second delay input element 27 to read the node of the fixed memory 23, transmits the numerical code from the memory cell, whose address is determined by the contents of the shift register 20, to the static register 24, preparing the recording signal generation unit to shaping the next switch in the recording signal. The values of the codes recorded in the node 23 of the permanent memory are determined by the desired functional relationship between the ratios of the durations of adjacent intervals adjacent to the modulated

6996. ten

by code unit (signal of type -. BBfiM), made according to the scheme in FIG. 4, works as follows.

An information code, accompanied by a synchronization pulse, is fed to the input of the block and is recorded on the shift register 20. The output of the high bit of the shift register is 20

JQ is connected to one of the inputs

15

20

25

thirty

.35

40

45

0

five

And 22, the second input of which receives a synchronization pulse delayed in time on the delay element 21. If a code unit is recorded at this moment in the higher order of the shift register 20, then the delayed synchronization pulse, passed through the AND 22 element, is fed to the input of the second delay element 27 and to the input of the pair-allelic code writing to the counter 25. Under the influence of this digital signal The code from the static register is rewritten to the counter 25. As a result, the first input of the AND 28 element produces an enable signal, which is valid until the counter 25 has non-zero states (the OR element 26 provides the transmission of second signal as long as at least while one of the bits of the counter 25 will be written to the coded unit). Now, the input of the counter 25 receives the synchronization frequency from the input of the block, the transfer of the counter into a sequence of successive states. As soon as the counter completes the counting cycle, an overflow signal is generated at its output, and the enabling signal disappears at the output of the AND 28 element. The overflow signal switches the state of trigger 29, providing a recording signal with a compensating additional phase modulation.

In parallel with this, a synchronization pulse, having passed through the second delay input element 27 to read the node of the fixed memory 23, transmits the numerical code from the memory cell, whose address is determined by the contents of the shift register 20, to the static register 24, preparing the recording signal generation unit to shaping the next switch in the recording signal. The values of the codes recorded in the node 23 of the permanent memory are determined by the desired functional relationship between the ratios of the durations of adjacent intervals adjacent to the modulated

switching in the recording signal, and the amount of additional phase modulation.

In the considered variant, the functional connection is established approximately logarithmic, the recorded codes are given in Table 2:

The formation of the recording signal in the form of a sawtooth voltage (the circuit of the recording signal driver is shown in Fig. 5).

The information code received from the input of the block is sequentially written to the shift register 30 under the influence of signals from the output of the divider 33 of the frequency of the synchronization pulses, also fed to the input of the delay element 35.

The operation cycle of the block begins with the arrival of the code unit in the high bit of the shift register 30.

Depending on the content of its previous bits, the signal from the output of delay element 35 can pass either through AND 36 or through AND 37 or both (if there are code units in both lower digits of the shift register 30) and start accordingly , or trigger 38, or trigger 39, DIBO both together. As a result, either the pulses of the synchronization frequency and the input of the block, or from the outputs of dividers 31 and pi, 32 of this frequency, pass through the output of the ZI-OR 34 element. The dividers 31 and 32 in the present embodiment have division factors 2 and 3, respectively. The pulses from the output of the ZI-OR 34 element are fed to the input of the counter 41. The positivity of the digital codes, taken from the outputs of the counter 41, is converted into voltage by the converter 42, ensuring the formation of the voltage across the voltage of the voltage generator. The auxiliary input of the converter 42 provides a signal from the output of the counting trigger 40. Under the action of this signal, the signals taken from the outputs of the counter 41 are switched from direct to inverse. Since the switching of the trigger 40 occurs on the overflow signal of the counter 41, in the adjacent intervals the direction of the signal change at the output of the converter is reversed.

In addition, the overflow signal from the counter 41 causes a reset

0

five

0

five

0

five

0

five

0

five

at. the initial state of the flip-flops 38 and 39, as a result of which the cycle of operation of the recording signal-forming block in the form of a saw-tooth voltage is completed.

Claims (3)

1. A multi-track. Digital magnetic recording method based on switchings in the recording signal for each recorded code unit of the encoded information for each working track to form a predetermined, periodically repeated recording format, characterized in that in order to expand the amount of recorded information from control the quality of information and the possibility of its correction; for each working track, they record a signal, code unit, signals of one or several bytes of information recoded into ten and digital words ending in a code unit and containing no more than two zeros are further, while the recoded bytes of the control code for the information bytes written along the remaining work tracks also write two code parity characters of the number of code units written to odd and even places of the recoded information, and an additional code unit, then in parallel with two lines of magnetic recording, the parity symbols of the number of code units for each line of magnetic fields are written Recording of the recoded information is not performed at the positions of unused bits of signal switching. 2. A device for multi-core digital magnetic recording, containing a source of information and control signals, serially connected shapers and recording signal amplifiers for the number of working tracks and a block of magnetic heads, which, in order to expand the amount of recorded information with quality control information and the possibility of its correction, it is equipped with a code converter, a buffer orthogonal storage block and a reading address counter, while the source of information and control signals and first and second outputs connected to respective inputs of the converter code, the third input signal to the input buffer write orthogonal memory block, and fourth output - with the combined inputs the read address counter and the signal input of the read orthogonal memory unit, the read address counter their outputs. connected in parallel to the input addresses of the buffer orthogonal storage block and code converter, three groups of inputs of which are connected respectively with a group of information inputs and a group of inputs to the address of a record of the orthogonal storage block and in parallel with a group of information outputs of this block with inputs of write signal drivers, code converter contains a counter with a serially connected counter to it, a trigger, a delay element, the output of which is connected to the counter input, and the input, Integrated with the input of the constant memory unit is the clock input of the converter, the first inputs of the first group of elements I, connected in parallel to the inputs of the first decoder, are connected to the outputs of the counter, which together with the output of the counting trigger form the first group of outputs A single converter, the outputs of the first decoder are connected to the control inputs of the multi selector, two groups of inputs of which are connected respectively to the first group of inputs of the converter and the outputs of the first register of trigger triggers, output Multi-selector dyes are connected to the address inputs of a permanent memory unit, the outputs of which are divided into two groups, one of which, together with the outputs of the first group of elements I, is connected to the inputs of the first register of counting triggers, and one of the outputs is additionally connected to the second inputs of the first the group of elements And, the second group of outputs, connected with the inputs of the second register of counting flip-flops, is the second group of outputs of the code converter; to the outputs of the second. register counting flip-flops are connected in series static rd register and the second group of AND gates, whose outputs are a third group of code converters outputs, a second set input code converter | Q g 20. 25 so Q ds 55 connected to the inputs of the second decoder-i torus, the output of which is connected to the control inputs of the second group of the second group of elements, And, ( 3. The device according to claim 2, comprising a shift register whose inputs are the driver inputs, the OR element, two delay elements and a counting trigger, characterized in that the recording signal driver is additionally equipped with a fixed memory unit, a static register, a counter and two elements And, while the clock input of the imager is additionally connected to the input of the first delay element, the output of which is connected to the first input of the first element AND, the second input of the shift register connected to the output of the last bit a, the remaining outputs of the bits of which are connected to the inputs of the reading address of the block of permanent memory, the outputs of the block of constant memory are connected to the inputs of writing a static register, the outputs of which are connected to the inputs of the parallel counter of the initial state of the counter, the outputs of the bits connected to the inputs of the element OR, the output of the first element AND is connected to the input of the control of parallel recording of the counter and the input of the second delay element to the output of which the input of the reading control of the memory block is connected, the input of the clock frequency ormirovatel it connected to the first input of the second AND gate, a second input coupled to an output of the OR gate, and an output - with a counter counting input, the output of which is connected to the input of the flip-flop counting. 4, The device according to claim 2, comprising a shift register whose input is an information input of a former, a counting trigger, a delay element, a ZI-NL element and a digital-to-voltage binary converter, wherein the former of the recording signal generator is additionally equipped with a three divider clock, a counter, two And elements and two triggers, while the combined inputs of all the clock frequency dividers are synchronization inputs of the driver, to which one of the inputs is also connected ZI-OR element, one of the inputs of each of the remaining two schemes AND is connected respectively to the outputs of the first and second clock frequency dividers, the output of the third clock frequency divider is connected to the clock input of the shift register and the input of the delay element, the output of which is connected to the first inputs of the first and the second elements And, the second inputs of which are connected respectively with the outputs of the first and second bits of the shift register, and the combined third inputs - with the output of the third bit of the shift register, the outputs And in setting inputs connected to the corresponding two triggers reset inputs which are connected to the input of the counting trigger and connected to the output of the counter, the first outputs of the triggers are connected to the second inputs of the first and second circuits. And the ZI-OR element, and the second outputs of the triggers are connected to the two inputs of the third circuit AND the ZI-OR element , the output of the ZI-OR element is connected to the input of the counter, the outputs of which are connected to the corresponding inputs of the binary-to-voltage converter, the auxiliary input of which is connected to the output of the counting trigger, and the output is the output of the signal conditioner and records. Table 1 Note. The codes in the table are written in octal form. Sh Leremdirobann / th date of insormation Pere (oddro6annyi byte control code  (parity of recombined transformation Cmpof parity codes magnetic records Current & Record Code Code Units 1 Table 2 FIG. 2