SU1601607A1 - Device for selecting standard time signals - Google Patents

Abstract

This invention relates to time stamping and timing. The aim of the invention is to increase the noise immunity of the timeout signal. The device for selecting time calibration signals contains detector 1, limiter 2 signals on the upper and lower levels, shift register 3, multiplexer 4, first pulse counter 5, comparator 6, pulse driver 7 corresponding to the leading edge of the signal, second and third counters 8 and 9 pulses, the first and second additional counters 10 and 11 pulses, an additional comparator 12, a generator of 13 pulses and a driver of 14 sequences of clock pulses. In the device for the selection of time calibration signals, a positive effect is achieved by applying digital methods for optimal signal detection and implementing an automatic setting of the current time hour by demodulating the information contained in the sixth pulse of the signal to verify the informationalized time. 1 il.

Description

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The invention relates to the field of time allocation and calibration,

The aim of the invention is to increase the noise immunity of the time verification signal.

The drawing shows a structural electrical circuit of the device for selecting time calibration signals.

The device contains a detector 1, a limiter 2 signals on the upper and lower levels, the shift register 3 multiplexer 4 the first counter 5 pulses, the comparator 6, the driver 7 pulse corresponding to the leading edge of the signal, the second and third counters 8 and 9 pulses, the first and second additional counters 10 and 11 pulses, an additional comparator 12, a generator of 13 pulses and a driver of 14 clock sequences.

The device for selecting time verification signals operates as follows.

The input signal is detected in detector 1 and, after being formed in limiter 2, is fed to shift register 3, where the signal is discretized in time. In this case, the envelope of the input signal (six video pulses and six pauses) turns out to be divided into 120 elements with a length of 50 m each at a sampling frequency (frequency of advancement of information on the shift register) of 20 Hz. The sampling signal is generated by dividing the frequency of the 13 pulses in the shaper 14, From the outputs of the bits of the shift register 3, information in the parallel code goes to multiplexer 4, which switches the outputs of the shift register 3 to the input of the first counter 5, the polling frequency of multiplexer 4 is selected commutation of all bits of register 3 shift for the duration of one element of the signal. The multiplexing operation is preceded by multiplying the values of the bits of the 3 shift register by weighting factors, which in this case have two values: + and -1, which corresponds to the transmission of significant bits in direct or inverse form and thus degenerates into the connection of the multiplexer inputs

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4k direct or inverse outputs of the bits of the register 3 shift.

The result of the weight summation is accumulated in the first counter 5, the binary unit at its control input increasing the number stored in the first counter 5 by one, and the binary zero decreasing it by the same amount. Thus, for the total analysis time (T 6 s), if there is an input at the input of the device for the selection of time calibration signals, the time calibration signal in the first counter 5 is set to 60, the counter state

5 is compared with a predetermined threshold in the comparator (S, the output of which serves to enable the setting of the hour of the current time or zeroing of the external counter,

To determine the value of the current hour transmitted in the sixth radio pulse, a digital pulse-width demodulator is used, built on the second additional counter 11 and acting on the principle of counting the number of periods of the reference frequency for a given time, which in this case is set by the second counter 8, Relative Threshold inside each partial pulse is set using an additional comparator 12 connected to the output of the third counter 9, and in the usual case equal to 0.5, which corresponds to the mode Do symmetric channel with additive white noise.

The first additional counter 10 serves to prevent the sixth radio pulse from being triggered during the first 100 ms. The second additional counter 11 counts the number of 20-ms intervals placed in the variable part of the sixth radio pulse. The signal from the pulse-width demodulator in a parallel code is fed to the additional outputs of the device. The installation of the second and third counters 8 and 9, as well as the first and second additional counters 10 and 11, is reset to the initial state by a signal taken from the output of driver 7,

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 the invention

A device for selecting time calibration signals, comprising a series-connected detector and a limit signal gel at the upper and lower levels, a first pulse counter and a comparator connected in series, as well as a pulse driver corresponding to the leading edge of the signal, a pulse generator and the second and third pulse counters, characterized in that, in order to increase the robustness of the time calibration signal, an additional companion is connected in series, the first and second additional ADDITIONAL counters impul1

The serially connected shift register and multiplexer, the output of which is connected to the control input of the first pulse counter, as well as the clock pulse shaper, while the output of the signal limiter at the upper and lower levels is connected directly to the information input of the shift register and through the pulse shaper, corresponding

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to the leading edge of the signal, to the setup inputs of the second and third pulse counters and the first and second additional pulse counters, the output of the pulse generator is connected to the input of the driver — sequences of clock pulses, the first, second, third and fourth outputs of which are connected respectively to the clock inputs of the register the shift and the first pulse counter, the control input of the multiplexer and the combined clock inputs of the second and third pulse counters and the second additional pulse counter lsov, account resolutions Display resolution input is connected to the output of the second pulse counter, and the third pulse counter output is connected to an additional input of the comparator, wherein the comparator outputs and the second additional pulse counter are respectively output and an additional 5 GOVERNMENTAL device outputs.

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Claims (1)

FORUM OF THE INVENTION A device for selecting signals for checking the time verification, comprising a serially connected detector and a signal limiter at the upper and lower levels, a first pulse counter and a comparator connected in series, as well as a pulse shaper corresponding to the leading edge of the signal, a generator pulses and the second and third pulse counters, characterized in that, in order to increase the noise immunity of the allocation of the signal of verification of time, introduced in series connected additional comparator, the first and second additional pulse counters, connected in series to the shift register and the multiplexer, the output of which is connected to the control input of the first pulse counter, as well as a sequence generator of clock pulses, while the output of the signal limiter at the upper and lower levels is connected directly to the information input of the shift register and through a pulse shaper corresponding to the leading edge of the signal to the installation inputs of the second and third pulses of pulses and the first and second of additional pulse counters, the output of the pulse generator is connected to the input of the pulse sequence generator, the first, second, third and fourth 10 outputs of which are connected respectively to the clock inputs of the shift register and the first pulse counter, the control input of the multiplexer and the combined clock inputs of the second 15 and third counters pulses and a second additional pulse counter, the input of the resolution of the account of which is connected to the output of the second pulse counter, and the output of the third etchika pulses 20 is connected to an additional input of the comparator, wherein the comparator outputs and the second additional pulse counter and are respectively output dopolnitel25 GOVERNMENTAL device outputs. .