SU1598030A1 - Device for protecting uninterrupted-supply unit - Google Patents

Abstract

The invention relates to electrical engineering. The purpose of the invention is to increase the reliability of the device. The device consists of two identical channels, each of which contains a node 1, 2 delays and interlocks with interlocking and disconnecting outputs, the first element IS-HE 3, 4, an output connected to the first input of the second element IS-HE 5, 6, the second input of which connected to the blocking output of node 1, 2 delays and blocking, the third element is NOT 7, 8, the first input of which is connected to the output of the second element IS-NOT 5, 6, and the second input is connected to the disconnecting output of node 1, 2 delay and blocking , the fourth element AND-NOT 9, 10, the first input of which is connected to the output t Another element of the IS-NE 7, 8, element 11, 12 of the isolating, the input of which is connected to the output of the second element of the AND-NOT 5, 6, shaper 13, 14 of the blocking pulses, the input of which is connected to the output of the element of isolating 11, 12, and the outputs of the formers 13, 14 of the blocking pulses of the first and second channels are connected to the second input of the fourth elements AND-HE 10, 9, respectively, of the second and first channels. The outputs of the fourth AND-HE elements 9, 10 are the device outputs, and the inputs of the first AND-NE elements 3 and 4 of the delay nodes 1 and 2 and the locking are the device inputs. The device has increased reliability by eliminating common elements for each of the two channels and introducing decoupling elements, which allows for maintenance work on separate channels. 4 il.

Description

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The invention relates to electrical engineering and can be applied in protection devices for redundant autonomous sources based on current inverters.

The purpose of the invention is to increase reliability.

FIG. 1 shows a block diagram of a device for protecting an uninterruptible power supply unit; in fig. 2 is a block diagram of the limiter overload duration; in fig. 3 - diagrams of operation of the device during a short circuit in the load; in fig. 4 - the same. in case of an accident in the inverter of the second channel of the uninterruptible power supply unit.

The device (Fig. 1) consists of two identical channels, each of which contains a limiter 1 (2) of the duration of the overload with the first storing signal overload and the second forming the signal about the end of work on overload outputs, the first element IS-NOT 3 (4), output connected to the first input of the second element AND-NOT 5 (6), the second input of which is connected to the first output of the limiter 1 (2) of the overload duration, the third element AND-NOT 7 (8). the first input of which is connected to the output of the second element AND-NOT 5 (6), and the second input - to the second output of limiter 1 (2) of the overload duration, the fourth element of AND-HE 9 (10), the first input of which is connected to the output of the third element AND - NOT 7 (8), element 11 (12) of isolation, the input of which is connected to the output of the second. AND-NE element 5 (6), shaper 13 (14) of the blocking pulses, input of which is connected to the output of element 11 (12) ZK, and the output of the formers 13 and 14 of the first and second channels are connected to the second inputs of the fourth elements AND-NOT 10 and 9, respectively second and first channels. The outputs of the fourth elements AND-NOT 9. and 10 are the outputs of the device, and the inputs of the first elements AND-NOT 3 and 4 and the inputs of the limiters 1 and 2 of the overload duration are the inputs of the device.

The limiter 1 (2) of the overload duration (Fig. 2) of each channel contains a trigger 15, the first output of which is connected to the first delay element 16, and the second output head is the first output of the limiter 1 (2) overload duration, the element AND NOT 17, the first the input of which is connected to the output of the delay element 16, and the second input is connected to the output of the HE element 18, the second delay element 19 with the inverting output, whose input is connected to the output of the delay 16, and the inverting output to the trigger reset input 15. the input of the element is NOT 18 is connected to inform Zion Valid Trigger 15, wherein the data input flip-flop 15 is input, and the output of AND-NO element 17 - the second output of the limiter 1 (2)

overload duration.

The device works as follows.

The first inputs of the elements AND-NOT 3 and 4 receive signals IBX.I, 1 in. 2 with the threshold

elements controlling the input currents of the first and second parallel channels of the uninterruptible power supply unit, each of the channels of which consists of a rectifier, an inverter and a high-speed contactor. The second inputs of the elements AND-NOT 3 and 4 receive the generalized failure signals of the inverters Uebix.ii ivyh.2 respectively the first and second channels of the unit uninterrupted

nutrition To generate these signals, threshold elements are used to monitor the voltage of the inverters on the switching capacitors and the thyristor state sensors that monitor the correct operation of the inverter thyristors. The inputs of the limiters 1 and 2 receive signals 1N from the threshold elements that control the current in the load.

In the normal mode, on the first (Fig. Over), on the second (Fig, 36) inputs of the elements AND-NOT 3 and 4, on the inputs (Fig, Sv) and on the first (Fig. Zd) and the second (Fig. Gc) outputs limiters 1 and 2, at the outputs of the elements

AND-NOT 5 and 6 (Fig. Z) signals 1 are generated. Signal 1 is also generated at the outputs of the elements AND-HE 9 and 10 (FIG. 3H). In a short circuit in the load at time ti, to the information input of the trigger 15

Both limiters 1 and 2 receive zero (with single-phase short-circuit impulse) signals (Fig. Sv). The trigger 15 in both the limiters 1 and 2 changes its state, on its first output 1 is formed (Fig. Ze), on the second O (Fig. Rear). The signal O from the second output of the trigger 15 enters the second inputs of the inputs NAND 6 and 5 and blocks the passage to the output of the alarm device О .Uebix.l,

ivyh.2 (Fig. 36), received at time t2 at the second inputs of the elements AND-NO 3 and 4 and inverted elements AND-NOT 3 and 4 (Fig. Zg). The signal 1 formed at the first output of the trigger 15 (Fig. 3) is delayed during the time ti-ta by the delay element 16 and at the time ta at the first input of the AND-NE element 17 a single signal is formed (Fig. 3b).

If at time t3 the alarm (zero) signals (fig. Sv) did not disappear, then

inverted by the element HE 18 single signals (Fig. 3), arriving at the second input of the element AND-E E 17, ensure the formation at the output of the element AND-HE 17 a zero pulse (FIG. 3k). Zero im-. The pulse is inverted by the NAND element (FIG. 3m) and goes to the first inputs of the NAND elements 9 and 10. Signals 1 from the outputs of elements 6 and 5 also go to elements 11 and 12 of the isolator, where they are potentially spread through the drivers 13 and 14 arrive at the second inputs of the elements AND-NOT 10 and 9. Since during the entire short circuit time at the output of elements 5 and 6 signal 1 is present (Fig. 3i), the drivers 13 and 14 do not change their state and Signal 1 is present at the second inputs of the AND-HE elements 9 and 10 (Fig. 3L). As a result, at time t3, a pulse signal O is generated at the outputs of the device, which ensures the shutdown of fast contactors by time t / i. The inverters go into idle mode, their output voltages are restored and, at time ts, signals 1 are generated at the second inputs of the AND-HE elements 3 and 4 (Fig. 36). If the duration of the short circuit in the load is less than the delay time of the element 16 (ti-t3). then, at the second input of the NAND-17 element, single signals are not generated, and therefore, at the output of the NAND-17 element, a zero pulse is not generated. As a result, the high-speed contactors will not shut down, the load will not be de-energized, and the trigger 15 at time t3-t6, determined by delay element 19, will return to its initial state (Fig. A, F) with pulse signal O from the output of delay element 19 (Fig. Zo). The delay time t3-t6 must not be less than the time of the output of the inverters to the nominal mode after the end of the short circuit in the load. The duration of the pulse signal O at the output of the element 19 te-t is determined by the total delay time of the elements 16 and 19 on the signal O from the first output of the trigger 15.

The difference ti-t2 in the time of arrival of the alarms 1n and Vyvh 1, ivykh.2 (fig. Sv, d) is due to the fact that the threshold elements that provide the output of the signals UvihL, ivykh.2 are connected to the switching capacitors of the inverter, and not load.

In case of an internal accident, for example, in the inverter of the second channel of the uninterruptible power supply unit at the moment of time ti, the signal O arrives at the second input of the first, AND-NO 4 element (Fig. 4a). This signal is inverted by the AND-NO 4 element (FIG. 46) and is fed to the first input of the AND-NOT 6 element. Since the second input of the AND-6 element at this time contains a signal 1, then the output of the AND-6 element is formed signal O (fig. 4d), which causes the formation of signal 1 at the output of the element AND-HE 8 (fig. 4e) This signal is fed to the first input element AND-NOT 10,

0At the same time, the signal O from the output of the element AND-NOT 6 enters the element 12, is potentially untied by it and enters the input of the imaging unit 14, which forms O for s-xz signal during the time (Fig. 4e). This signal is fed to the second input element AND-NOT 9.

In case of internal accidents in one of the inverters, due to the fact that the controlling threshold elements have a finite value of speed, the emergency processes of one inverter lead to a deviation of the output voltage in a working inverter beyond the allowable limit and to output at time t2 by the corresponding threshold element of the signal A. This signal arrives at the second input of the element AND-HE 3 (Fig. 4c), is inverted twice by the elements AND-HE 3 and 5, is potentially dissociated by element 11 and enters the generator 13. The latter forms of time t2- t-i signal O (Fig. 4g), which is supplied to the second input of AND-NO element 10. Simultaneously, the signal G with the output element 5 AND-element is inverted

5 AND-NOT 7 (FIG. 4i) and arrives at the first input of the element AND-NOT 9. As a result, during the time ti-t2, signal 1 is present at both inputs of the element AND-NOT 10 and a pulse is generated at the output of this element

0 signal O (fig. 4z), which leads to the disconnecting of the high-speed contactor of the second channel of the uninterruptible power supply unit and thereby to disconnecting the failed inverter from the load.

5 of the fact that the O signal arrives at the second input of the NAND 9 element earlier (Fig. 4e, ti) than the signal 1 at the first input of the same element, the O signal is not generated at the output of the NI 9 element and a working inverter is fast the contactor is not disconnected from the load.

The blocking pulse shaper can be made on the basis of a single-vibrator with a restart, which

5 allows the generation of a single blocking pulse signal upon arrival of pulsed signals at the device inputs, which eliminates in this case the possibility of generating the signal O in the first channel. The duration of the blocking signal is determined by the time of disconnecting the high-speed contactor and the time of the output of the inverter of the healthy channel of the uninterruptible power supply unit to the nominal mode.

Thus, the proposed device has increased reliability due to the exclusion of common elements for each of the two channels and the introduction of isolation elements, which makes it possible to carry out maintenance work on separate channels,

Claims (1)

Formula of the Invention A device for protection of an uninterruptible power supply unit consisting of two parallel channels, each of which includes an inverter, containing a first overload duration limiter with a memory overload signal and generating a signal about the end of work on overload outputs and two identical channels each from the first element AND-NOT, the output connected to the first input of the second element AND-NOT, the second input of the second element AND-NOT of the first channel is connected to the memory signal ne egruzki output of the first limiter overload duration, an output of second AND-NO element is connected to both channels of the first input of the third AND-NO element of the corresponding channel, the second input of the third AND-NO element is connected to the first channel signal the end of the forming operation to output overload the first limiter overload duration, the output of the third element AND-NOT of each channel is connected to the first input of the fourth element AND-NOT of the corresponding channel, the first and second inputs of the first AND-NOT element of each channel are connected to the terminals for connecting the input current control unit and unit generating generalized signals of inverter failures of its own channel, and the input limited duration of the overload of each channel is connected to the terminal for connecting the load current control unit, characterized in that reliability, it is equipped with a second overload duration limiter that stores the overload signal and generates a signal about the end of the work to overload outputs, two blocking impulses and two isolators, the second input of the second element IS-NOT of the second channel is connected to the memory signal the overload output of the second limiter overload duration, the second input of the third element IS-NOT of the second channel is connected to the output of the second ogre that forms the signal of the end of work for overloading The overload duration indicator, and the second inputs of the fourth AND-NOT elements of the first and second channels are connected via blocking impulses and isolators to the outputs of the second AND-NE elements, respectively, of the second and first channels. J 2 at || t, tt, | "" SHIGA