SU1597763A1 - Analyzer of spectrum of parallel action - Google Patents

Abstract

The invention can be used in radio engineering, acoustics, medicine. The purpose of the invention is to improve the accuracy of analysis - the introduction of 25 analog signals, 5 counters, 6 pulses, trigger 17, pulse formers 15 and 16 pulses, a digital switch 12, a digital readout unit 13, a digital-to-analog converter box 14 with upstream registers, programmable memory block 7 and generator 18 paired pulses. The spectrum analyzer also contains a synthesizer 8 frequencies, a wideband differential amplifier 20, N selective channels consisting of adjustable band-pass filters 21-23 and amplitude detectors 26-28, a switch 24 analog signals, a pulse counter 4, a digital oscilloscope 30, a synchronization unit 29, shaper 3 reset pulses, three-pole switches 1, 2, attenuator 19, shaper 9, synchronous detector 10 and an integrated analog-to-digital converter 11. 1 Il.

Description

The invention relates to information-measuring equipment, in particular, to the field of parallel spectral analysis and can be used in radio engineering, acoustics, medicine, ultrasonic Defectoscopy and echo location, in closed-type signal synthesizers, etc.

The purpose of the invention is to increase the accuracy of the analysis.

The drawing shows a structural diagram of a spectrum analyzer parallel action. ''

The analyzer contains the first and second switches 1 and 2, a shaper of 3 reset pulses, the first, second and third counters of 4-6 pulses, a programmable memory unit 7, a digitally controlled synthesizer of 8 frequencies, a shaper of 20, a synchronous detector 10, integrating analog-to-digital converter 1 1, switch 12 of digital signals, digital block 13 of subtraction, block 14 of digital-to-analog converters 25 with upstream registers, first and second formers 15 and 16 pulses, trigger 17, generator 18 pair pulses, attenuator 19, wide axle differential usi- jq divisor 20, the first K-th and N-th polling tunable filters 21-23, the first and second switches 24 and 25 are analog signals, the first

K-th and N-th amplitude detectors 26-28 synchronization block 29 and a digital oscilloscope 30, while the input terminal of the parallel spectrum analyzer is connected to the first input of the first three-pole switch 1, the output of which is connected to the direct input of the broadband differential amplifier 20, inverse input which through the attenuator 19 is connected to the output of a digitally controlled synthesizer 8 frequencies, and to which are connected serially connected shaper 9, a synchronous detector 10 and an integrating analog-digital conversion The device 11, the output of the broadband differential amplifier 20 is connected to interconnected inputs of N selective channels, consisting of series-adjustable tunable bandpass filters 21-23 and amplitude detectors 26-28.

The inputs of the first switch 24 of the analog signals are connected to the outputs of the amplitude detectors 26-28, the output of the first switch 24 of the analog signals is connected to the input of a digital oscilloscope 30, the synchronization input of which is connected to the main output of the synchronization unit 29, additionally. the output of the synchronization unit 29 is connected to the counting input of the first counter 4 pulses, the outputs of which are connected to the control inputs of the first switch 24 of the analog signals.

The zero-setting input of the first 4 pulse counter is connected to the output of the reset pulse generator 3, which is connected to the output of the second three-pole switch 2, the first input of which is connected to the power terminal, and the second, like the second input of the first three-pole switch 1, is connected to the ground bus, the first and the second three-pole switches 1 and 2 are combined for control, i.e. their manual controls are rigidly interconnected, between the outputs of the integrating analog-to-digital converter 11 and the control inputs of the bandpass filters 21-23 are connected in series connected switch 12 of digital signals, a digital subtraction unit 13 with upstream registers and a block 14 of digital-to-analog converters with upstream registers, controlling the input of the switch 12 of the digital signals and the first control input of the digital subtraction unit 13 are combined and connected to the output of the first driver 15 pulse in inverse output flip-flop 17 is connected to the second control input of the digital subtraction unit 13, the flip-flop output line 17 is connected to the input of the second pulse shaper 16, the output of which is connected to the counting input of the second counter 5 with the synchronizing pulses and the input of the generator 18, the paired pulses. The output of the latter is connected to the counting input of the third counter 6 pulses, to the input of the first driver 15 pulses and to the counting input of the trigger 17, the installation inputs ”0 trigger 17, the second and third counters 5 and 6 pulses are combined and connected to the output of the shaper 3 of the reset pulses, outputs third pulse counter 6 — through a programmable memory unit 7 is connected to the control inputs of the frequency synthesizer 8, the outputs of the second pulse counter 5 are connected to the control inputs of the same name in the registers of block 14 of the digital-to-analog converters STUDIO and second switch 25 analog signals. The input of the zero channel of the switch '25 is connected to a common bus, the remaining N inputs are connected to the outputs of the bandpass filters 21-23 of the corresponding selective channels. The output of the second switch 25 of the analog signals is connected to the signal input of the synchronous detector 10.

The parallel spectrum analyzer operates as follows.

The analyzed signal U (t) is fed to the first input of the first three-pole switch 1, the second input of which is connected to the ground bus. In the initial state, the three-pole switches 1 and 2 are in the position shown in figure 1.

When you turn on the three-pole switches 1 and 2, the signal 1 is fed to the direct input of the broadband differential amplifier 20. The supply voltage U _n through the three-pole switch 2 is supplied to the shaper 3 of the reset pulses. At the output of the latter, a signal is generated that sets the trigger 17 to 0 and the counter 4-6 pulses.

Code 0, arriving, for example, from the outputs of the third counter 6 pulses to the inputs of the programmable memory unit 7, provides the appearance on the outputs of the code block corresponding to the maximum value of the frequency of the digitally controlled synthesizer 8 frequencies. This code is fed to the control inputs of the frequency synthesizer 8 and provides the synthesis of the frequency signal f _{M (JKC} at the output of block 8. The output signal of the frequency synthesizer 8 of normalized amplitude U ^ _H goes to the attenuator 19, where it is attenuated in K _{ -times, i.e. to the desired level U ₀ = U _TOW / K ·. Then, the attenuated signal is supplied to the inverted input broadband differential amplifier 20, which amplifies the input signal together with 1 _{g of} K times.

The amplified test and analyzed signals are fed to the combined inputs of the bandpass filters 21-23 of the first, i-ro, and N-ro selective channels, respectively. At the same time6, but the code 0 of the output signal of the first counter 4 pulses sets the first switch 24 of the analog signals in the initial position for polling. Using the synchronization unit 29, the synchronization signal of the digital oscilloscope 30 and the serial signal of N channels of the spectrum analyzer are generated.

As a result of setting the second counter 5 pulses to 0, the second switch 25 of the analog signals is set to the position, respectively. corresponding to the connection of the analog input of the synchronous detector 10 to the ground bus, i.e. zeroing the last. At the same time, the supply of codes of numbers from the output of the digital block 13 of subtraction to the registers of the block 14 of digital-to-analog converters is prohibited.

Setting the trigger 17 to 0 ensures the start of the pulse shaper 16. At the output of the latter, a pulse of duration f is formed, sufficient to establish transients due to the supply of a test signal to the selective channels. The trailing edge of the output pulse of block 16 starts the paired pulse generator 18, and adds 1 to the counter 5 pulses. As a result, the code of the first channel is established at the output of the counter 5 pulses of _λ pulses, which connects the signal input of the synchronous detector 10 of the output signal a band-pass filter 21 of the first selective channel. At the same time, writing the code to the register of the first digital-to-analog converter of block 14 is allowed.

The pair pulse generator 18 generates a pair of short pulses spaced in time by £, sufficient to establish transients in the selective channels when the frequency of the test signal changes and the synchronous detector 11 is converted to the output signal code.

These pulses are fed to the input of the third counter 6 pulses. As a result of the receipt of the first pulse of the pair at the output of the counter 6, the code of the number 1 is set, which is supplied to the programmable memory unit 7. In accordance with this code, at the output of block 7, a code appears that sets the first value of the frequency f _{Wr of the} first test signal U _Rf (t) of the frequency synthesizer 8. Frequency f. the test signal corresponds to the final frequency of the detuning to the left of the center frequency of the band-pass filter 21 of the first selective channel.

The frequencies f _Ηι · and f _e · of each pair of test signals are selected outside the passband of the bandpass filters _,. set at 0.707 relative to the center frequency, based on the attenuation of the amplitudes of the test signals by 30-40 dV, i.e. _B1 f _{-> f e} + + ZJfj} / 2 and f _Mi <7 f _p-Z.) fj72, where f _fi | and f „· are the upper and lower frequencies of the i-th

NT pairs of test signals; χ / lf is the passband of the ith bandpass filter; f _oi is the center frequency of the band-pass filter i-ro of the selective channel.

The output signal U _{H <} (t) of the frequency synthesizer 8 through the attenuator 19 is fed to the inverse input of the broadband differential amplifier 20. The amplified analyzed and the first test signals are fed through a bandpass filter 21, to the inputs of the amplitude and synchronous detectors 26 and 10, respectively. The output signal of the amplitude detector 26 is proportional to the amplitude value of the analyzed signal at a frequency f _{e <} , is fed to the first input of the switch 24 of the analog signals. The output signal of the synchronous detector 10, controlled by a frequency signal f _Hl · and proportional to the amplitude value of the test signal U _H ; (t), attenuated due to the asymmetry of the amplitude-frequency characteristics of the band-pass filter 21, is fed to the input of an integrating analog-to-digital conversion. Calling 11. With his help specified. the signal is integrated (averaged) and converted into a code of the number N _{Н (} ·.

I

The first output signal is a generator. 18 pair pulses, delayed time Ό ₁ β of the first pulse shaper, is also used to control the operation of the switch 12 digital signals and registers of the digital subtraction unit 13. The delay time <ΐ ₀ is selected from the condition of reliable recording of the code of the number N _0Т in the register of block 13. The first delayed pulse allows passage of the code of the number N pa by 15

thirty.

through the switch 12 to the register of the reduced digital block 13 subtraction.

At the same time, the first output signal of the paired pulse generator 18 is fed to the counting input of the trigger 17, setting it to state 1 fia its direct output and state 0 at its inverse output. As a result, the code ”0 is received at the second control input of the registers of the digital subtraction unit 13, and the code” 1 is received from the output of the former 15 at the first input. The code is N ^. written to the register of the reduced digital block 13 subtraction. Passing the code of the number N ^, to the output of block 13 is prohibited. The signal is' logical. 1, received at the input of the second pulse shaper 16 from the direct output of the trigger 17, does not lead to the formation of a new trigger pulse, since it is triggered by a negative pulse front.

The second output signal of the generator 18 pair pulses, delayed for a time l ₀ , is supplied to the counting input of the third counter 6 pulses. As a result, at the output of counter 6, the code of number 2 is set, which is fed to the control inputs of the programmable memory unit 7. In accordance with this code, a code appears on the output of the memory block, which sets the second frequency value f _{01 of the} first test signal U _6r (t) of the 8 frequency synthesizer. The frequency f _{g1 of the} first test signal corresponds to the final frequency of the detuning to the right of the center frequency of the band-pass filter 21. of the first selective channel.

The output signal U _ei (t) of the frequency synthesizer through the attenuator 19 is also fed to the inverse input of the broadband differential amplifier

20. As in the previous case, the amplified analyzed and the first test signals are fed through a bandpass filter 21 to the inputs of the amplitude and synchronous detectors 26 th 10, respectively. The output signal of the amplitude detector 26, proportional to the amplitude value of the analyzed signal at a frequency f, is fed to the first input of the switch 24 of the analog signals. The output signal of the synchronous detector 10, controlled by a frequency signal f _fl1 proportional to the amplitude value of the test signal o

Ug, (t), weakened due to the asymmetry of the amplitude-frequency characteristic of the band-pass filter 21, is fed to the input of an integrating analog-digital converter 11. With it, the indicated signal is integrated (averaged) and converted into the code of the number Ν _β1 .

The second output signal of the generator is 18 pair pulses, delayed by the time C? in the first pulse shaper 15, sets the digital signal switch to a state in which the code of the number Ν _{β1 is} supplied to the inputs of the register of the subtracted digital subtraction block 13.

At the same time, the trigger 17 is transferred to the logical state “1 at its inverse output. The logical signal 1 from the inverse output of the trigger 17 is fed to the second control input of the registers of the digital subtraction unit 13, the first input of which after a while · ί? ₂ , the output signal of the shaper 15 is received. As a result, the code of the number-N ₀₁ is allowed to be written in the register of the subtracted digital block and the result of the subtraction, i.e. the code of the number N ₍ = N _{| jf} -N _e ,, at the inputs of the register of the first digital-to-analog converter of block 14.

At the output of the first digital to analog converter unit 14 a signal appears, for example, the voltage y _f = _SNf,; proportional to the difference of the codes of the number N _H1 and N _{e ,.} This voltage is supplied to the control input of the first band-pass filter 21, adjusting. its center frequency to the desired value.

The trailing edge of the output pulse of the trigger 17 starts the pulse shaper 16. At the output of the latter, an impulse of duration C, is formed. The trailing edge of this impulse, i.e. after a time ¢, sufficient to establish transients in the selective channel, the paired pulse generator 18 and the counter 5 are started for the second time. As a result, the second channel code is set to the output of the 5 pulse counter, which allows the output of the second filter of the band pass filter to be connected to switch 25 the signal input of the synchronous detector 10. The output code of the 5-pulse counter is also supplied to the control inputs of the registers of block 14 of the digital-to-analog converters, allowing recording the output code block 13 subtraction in the register of the second digital-to-analog Converter.

An 18 pair pulse generator generates a second pair of short pulses. The process of adjusting the center frequency of the bandpass filter of the second selective channel is repeated in a similar way. The capacity of the counter 5 pulses is equal to the number of selective channels, and the capacity of the counter 6 is equal to twice the number of selective channels.

Claims (1)

Claim A parallel spectrum analyzer containing a frequency synthesizer, a broadband differential amplifier, N selective channels consisting of tunable bandpass filters and amplitude detectors connected in series, a first analog signal switcher connected to the outputs of the amplitude detectors, a digital oscilloscope connected to the output of the first analog signal switcher, the first pulse counter connected with its outputs to the control inputs of the first switch of analog signals synchronization, connected by its main output to the synchronizing input of the digital oscilloscope, and an additional output - with the counting input of the first pulse counter, a reset pulse generator connected by its output to the setting input 0 of the first pulse counter, the first and second three-pole switches combined by control, the first inputs which are connected respectively to the input terminal of the device and to the power terminal, the second inputs are connected to a common bus, the output of the second three-pole switch is connected with the input of the reset pulse generator, the output of the first switch through a broadband differential amplifier is connected to the inputs of N selective channels connected to each other, as well as an attenuator connected between the inverse input of the broadband differential amplifier and the output of the frequency synthesizer, to which the former, synchronous detector, and integrating analog-to-digital Converter, characterized in that, in order to improve the accuracy of analysis and automation of the tuning process Olos filters, introduced the second _f switch of analog signals, the second and third pulse counters, the trigger, the first and second pulse shapers, the switch of digital signals, a digital subtraction unit, a block of digital-to-analog converters with upstream registers, a programmable memory block and a pair of pulse generator, the output of which is connected to the counting input of the third; a counter, to the counting input of the trigger and to the input of the first pulse shaper-jq, the output of which is connected to the control input of the digital signal switch and to the first control input of the registers of the digital subtraction unit; the second input of which is connected to the inverted output of the trigger, the direct output of the trigger through the second pulse shaper is connected to the input of the pair pulse generator and counted ™ input of the second pulse counter, the input of the O installation of which is connected to the inputs of the O ”setting of the third pulse counter, trigger and connected to the output of the pulse shaper reset, the outputs of the second pulse counter are connected to the control inputs of the same name registers block of digital-to-analog converters and second comm analog signal generator, the input of which the zero channel is connected to the ground bus, the remaining N inputs are connected to the outputs of the bandpass filters of the corresponding N selective channels, as the second analog signal switch is connected to the signal input of the synchronous detector, the output of the integrating analog-to-digital converter is connected to series-connected a digital signal switch, a digital subtraction unit, a block of digital-to-analog converters, connected to the control inputs by its outputs VAVO filters, the outputs of the third counter 'are connected to inputs of a programmable memory unit, the outputs of which are connected to the input of the frequency synthesizer.