SU1594459A1 - Logic circuit tester - Google Patents

Abstract

This invention relates to an instrumentation technique and can be used in the control of microcircuits. The purpose of the invention is to increase the reliability of the control by eliminating the false triggering of the control device in the event of a short circuit on the input of the control object to a single level. The logic probe contains terminals for connecting a monitored chip 1 and a reference chip 2, N channels, each of which contains analyzers 3 and 4, the element AND-NE 5, the RS flip-flop 6, the elements AND-OR 7 and 8, the comparison circuit 9, the element OR 10, button 11, RS-trigger 12, indicator 13. As a result of the introduction of elements 3.1, ..., 3.N, 5.1, ..., 5.N, 7.1, ..., 7.N and 8.1, ..., 8.N provides automatic detection of the input and output of the monitored circuit, the comparison of the values at its outputs and the elimination of false alarms when there is a break on the output of the reference chip, on the withdrawal of controlled - unit. 1 tab. 1 il.

Description

Order 2826

Circulation 562

Subscription

RCIIPI of the State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 4/5, Moscow, Zh-35 / Raushsk nab. 113035

Claims (1)

Claim Logic probe containing terminals for connecting the reference and controlled circuits, input "Na 1594459 initial setting, the OR element, the first Κδ-trigger, the indicator, n-channels, each of which contains the first analyzer, the second CZ-trigger, the reference element, the output of which is connected to the η-input of the OR element, the output of the last is connected to the 5-input of the first KZ-trigger, To-input of which is connected to the input "Initial installation", direct output - to the input of the indicator, 3-input of the second KZ-trigger15 20 Hera is connected to the output of the first scanner, K-input - to the input "Reset" the device, the K-input of the second K5-flip-flop, each of the (n-1) channels of the device, characterized in that, in order to increase the reliability of the control, a second U analyzer, the NAND element, the first is added to each of the η channels and the second AND-OR elements, the outputs of which are connected to the inputs of the comparison element, and their first inputs are connected to the direct output of the first KTrigger, the second input of the first I-IPI element is connected to the first input of the NAND element and the output of the second analyzer, the third input of the first element E-ILY is connected to the second entrance of the second The Y-OR element and the inverse output of the second short-circuit trigger, the fourth input of the first AND-OR element is connected to the input of the second analyzer and to the terminal for connecting a controllable microcircuit, the fifth input of the first AND-OR element is connected to the output of the AND-NES element, the second the input of which is connected to the third input of the firing element AND-OR and to the corresponding; 30 terminal for connecting the reference chip. 25 Signal Output Value and 1 .go and, and about ι 1 and ₀ and about 1.1 and, and, about 1 and ₀ and oh oh and and _t 10 about • · υ ₀ and _in about a 1 and, and ₀ 0 0 1 and and „ι о ι I 1 about 1 1 about 1 1 II o o 1 1 o 1 1 o o o 1 0 1 1 0 1