SU1594452A1 - Meter of parameters of complex resistors - Google Patents

Abstract

The invention relates to electrical measurements. The purpose of the invention is to simplify the process of checking the operability and troubleshooting of devices. The meter contains a power source, a measuring circuit having an adjustable reference measure, a measuring object and an amplifier, a measuring transducer including a series-connected synchronous detector and an A / D converter, a controlled voltage divider, a first switch, two fixed contacts, a controlled frequency divider, a generator pulses, a digital reading device, an automatic measurement range selection scheme including a division coefficient counter, a subband counter, a comparison circuit and lower bounds, setter of the upper and lower bounds code, the first element OR and the EXCLUSIVE OR element, comparison schemes of the upper and lower extreme states of the division coefficient counter, setters of the upper and lower extreme states code, the first and second elements AND, the first inverter, the second the element OR, the third element OR, the second inverter, the fourth element OR. The second frequency divider, the third element And, the second and third switches, the third inverter, the trigger, the fourth element And, the generator of test pulses are additionally introduced into the meter. The introduction of these elements provides for independent control of the component parts of the device, the organization of cyclic and step-by-step measurement, which simplifies the procedures for operability testing and troubleshooting. 1 hp f-ly, 5 ill.

Description

The invention relates to electrical measuring equipment and can be used in the construction of measuring impedance parameters.

The purpose of the invention is to simplify the process of testing and troubleshooting

devices by providing independent control of its components, organizing cyclic and search modes of operation,

Figure 1-3 shows the block diagram of the device; in fig. 4 and 5 - timing diagrams, shushustrigutsie work meter in the main mode Measurement and Debug mode.

The device contains a voltage source 1, a measuring circuit 2 having an output 3 and including a discrete-adjustable exemplary 4, an object 5 measuring and an amplifier 6, a measuring transducer 7, including a series-connected synchronous detector 8 and analog-to-digital converter (ADC) 9, the first switch 10, having a switching contact 11 connected to the input of the synchronous detector 8, and two fixed contacts 12 and 13, a controlled voltage divider 14, the input of which is connected to the output of the measuring circuit,the output is with a normally closed coke 13 of the switch 10, the normally open contact 12 of which, together with the reference input of the synchronous detector 8 and the input of the measuring circuit 2, is connected to the output of the current Ika 1 voltage, controlled by frequency frequency 15 and the pulse generator 16, the output of which connected to the signal input of a controlled frequency divider 15. The output of which is connected to the reference input of the ADC 9, a digital reading device (ACF) 17, the first input of which is connected to the output. A1Shch 9, the circuit for automatic selection of measurement limits 18, which includes the division factor counter 19, the subband counter 20, the output of which is connected to the control input of the exemplary measure 4 and the second input (control of the display of comma and dimensionality symbols) of the SFC 17, the top comparison circuit 21 and the circuit 22 comparisons below the boundaries, the first inputs of which are connected to the outputs of the ADC 9, the setting unit 23, the upper code and the setting unit 24, the lower boundary code, whose outputs are connected respectively to the second inputs of the comparison circuits, the upper 21 and lower 22 boundaries, ne OR 25 and EXCLUSIVE OR 26, the inputs of which are connected to the outputs of the comparison circuits of the upper 21 and even 22 boundaries, the comparison circuit 27 of the upper and the comparison circuit 28 of the lower extreme states of the counter 19 of the division factor, the first inputs of which are connected together but with the control inputs of controlled voltage dividers 14 and frequency 15 with the outputs of the split ratio counter 19, the upper code setting device 29 and the lower extreme cell code setting device 30

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e „5 35

45

50

55

The outputs of which are connected respectively to the second inputs of the comparison circuits of the upper 27 and lower 28 extreme states, the first 31 and second 32 elements of AND, the first inputs of which are connected respectively to the outputs of the circuits 27 and 28 of the upper and lower extreme states, the first an inverter 33, the output of which is connected to the second input of the second element AND 32, and the input together with the second input of the first element AND 31 and the reverse inputs of the counters of the division factor .19 and subbands 20 - with the output of the first element OR 25, the second, element OR 34 which entrances It is connected to the outputs of the first 31 and the second 32 ele. And the third element OR 35, the first input of which is connected to the output of the second element OR 34, the second inverter 36, whose input together with the prohibition input of the counter 19 counter of the division factor is connected to the output of the third element OR 35,. the fourth element OR 37, the output of which is connected to the inhibit input of the counter count of 20 subbands, the first input is connected to the output of the second inverter 36, and the second, together with the second input of the third element OR 35, is connected to the output of the EXCLUSIVE OR element 26, the second divider 38. the input of which, together with the clock inputs of the dividers 19 and subbands 20 counters, is connected to the output of voltage source 1, the third element AND 39, the first input of which is connected to. the output of the second frequency divider 38, and the second input - with the output of the element CIRCELSHIPNEYE OR 26, the second switch. 40, the changeover contact of which is connected to the control input of the first switch 10, and the normally closed contact to the output of the third element I 39, the third switch 41, whose normally closed contact is connected to the supply potential, and the normally open contact to the common bus, the third inverter 42, the input of which, together with the third input (indication of the operation mode) of the control center 17 and the inputs for enabling the parallel recording of information of the dividers 19 counters and subbands 20, is connected to the changeover contact of the third switch 41, mp gager 43, the fourth element AND 44, the first input of which is connected to the output of the third inverter 42, and the output - to the counting input of the trigger 43, the output of which is connected to the normally open contact of the second switch 40, the second 40 and -the third 41 switches switching from synchronously test pulse generator 45, containing a second pulse generator 46, the input, whose synchronization Q is connected to the output of power supply 1, the fourth switch 47, whose normally closed contact is connected to the output of the second direct current generator 46 pulses, a 48-state counter, the counting input of which is connected to the changeover contact of the fourth switch 47, the fifth switch 49, the Start button 50, one of the contacts of which is connected to the common bus, and the other to the normally open contacts of the fourth-47 and fifth 49 switches, the flip pin of the 5th switch 49 is connected to the resolution enable input of parallel recording of the state counter 48, setting handles of the start 51 and end 52 states, the final state comparison circuit 53, the AND-NOT element 54, the output of which connected to the normally closed contact of the fifth switch 49; the first input is connected together with the prohibition input of the second rectangular pulse generator 46 to the output of the comparison circuit 53 of the final state of the measurement object 5. This voltage is applied to the control divider 14 of the voltage, and from the last code through the normally closed contacts 13 and 11 of the switch 10 to the input of the synchronous detector 8.

The detected feed voltage from the code of the synchronous detector 8 to the input A1 9 and is converted into a digital code. AJ.

The operation of the comparison schemes of the upper 2 and lower 22 limits is organized in such a way that

20

and the second input is with the output of the conversion of the ADC 9, the output of the initial code setpoint 51 is connected to the preset inputs of the state counter 48 and the division coefficient counter 19, as well as the installation input to the O flip-flop 43, the output of the end code adjuster 52 is connected With the first input of the final code comparison circuit 53 and the setup input to 1 flip-flop 43, the second input of the final status code comparison circuit 53 is connected together with the second input quad15 a logical unit in the case where the output code A value exceeds the value of the codes adatchik.a- E, respectively upper 23 and lower it to 24 codes. If the code fA is found in the working area of the ADC, then at the output of cx we compare the upper limit a logical O appears, and at the output of cx we compare the lower limit - logical 1

The presence at the output of the comparison circuits of the upper and lower limits of two O corresponds to the position of the output to da A below the working area of the ADC, and the presence of two 1 corresponds to the location of the AJ code above the working area of the ADC. The output signal of the SPLITTER OR 26 element allows or prohibits changing the states of the dividers 19 and 20 counters and subbands, and the inverter 36 ensures that only one of the counters is operating at the same time. The search for the ADC working area is possible without presetting in O the counters 19 and 20, the search direction Q is determined by the signal at the output of the first element OR 25. The search begins with an analysis of the state of the count 19 division factor. If he

is not at the extreme for the selected D.5 direction of the search state, the measurement zones are initially switched (controlled voltage divider 14) before entering the working zone or until the counter 19 is full

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TOGO element AND 44 and the input of the preschedule division. If the counter coefficient HnRTCM PUPTtJMtril 7P TmrTTTt; f attack olig l

20 counts with the output of the 48 states counter.

Measuring parameters of complex resistance works as follows, (Fig. 4),

When the source 1 is connected, a sinusoidal voltage is applied to the measuring circuit 2 at its output 3, a voltage proportional to the impedance occurs.

when the division factor is at the extreme for a given search direction from the base, then changing its states is prohibited and at the same time changing the states of the 20 -sub- counter, the ranges controlling the switching of the reference resistance measure 4, is permitted. Counters 19 and 20 are clocked by the operating frequency of voltage source 1.

object 5 measurement. This voltage is applied to the control divider 14 / voltage, and from the last code through the normally closed contacts 13 and 11 of the switch 10 to the input of the synchronous detector 8.

The detected voltage feeds from the code of the synchronous detector 8 to the input A1 9 and is converted into a digital code. AJ.

The operation of the comparison schemes of the upper 21 and lower 22 limits is organized in such a way that

Q 25

20

15 is the logical unit in the case when the value of the output code A exceeds the value of the codes given by the setpoint generator, respectively, the upper 23 and lower 24 codes. If the code fA is in the working area of the A / D converter, then logical 0 is output at the output of the upper limit comparison circuit, and logical 1 is output at the output of the lower limit comparison circuit.

The presence of the upper and lower limits of two O at the output of the comparison circuits corresponds to the position of the output code A below the working area of the ADC, and the presence of two 1 corresponds to the location of the AJ code above the working area of the ADC. The output signal of the EXCLUSIVE OR 26 element enables or disables the change of the states of the counters 19 and 20 of the division factor and the subbands, and the inverter 36 ensures the operation of only one of the counters. The search for the ADC working area is possible without presetting in O the counters 19 and 20, the search direction Q is determined by the signal at the output of the first element OR 25. The search begins with an analysis of the counter 19 state of the division factor. If he

is not at the extreme for the selected .5 direction of the search state, then the measurement zones are initially switched (controlled divider 14 into straps) before entering the work zone or until the counter 19 is full5

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division factor. If the division ratio counter. If the counter is

when the division factor is at the extreme for a given search direction from the base, then changing its states is prohibited and at the same time changing the states of the 20 -sub- counter, the ranges controlling the switching of the reference resistance measure 4, is permitted. Counters 19 and 20 are clocked by the operating frequency of voltage source 1.

The subband counter 20 sequentially changes the value of the discrete-adjustable resistance measure 4 until it enters the working area of the ADC or the combination changes at the output of the comparison circuits 21 and 22 to the opposite (i.e., two 0 appear instead of two 1, or vice versa). This means: that the working area of the ADC is omitted and to; it must be returned in the opposite direction. At the output of the first: element OR 25, a signal appears

corresponding to the search in the reverse direction, and since the state of the counter 19 of the division coefficient in this direction is not extreme, the change of its states is again allowed. The zones are switched in the direction opposite to the original one; getting the output code A to work; I feel the ADC area.

Therefore, the signal from the output of the €; - ment EXCLUSIVE OR 26 captures the selected sub-band and measurement zone.

In order to conduct, debug, and repair work, it is necessary to ensure the possibility of independent control of the device parts, the possibility of organizing the cyclical change of signals to check the correctness of their passage through the measuring path., The possibility of on-line measurement of the parameters of the complex resistance to check compliance with operaddy

The divider 38, the element 39 and the switch 40 ensure the operation of the instrument in the Measurement mode. During the selection of the measurement subband, only the voltage of the object is measured. This is accomplished by applying the logical signal O from the output of the EXCLUSIVE OR 26 element to one of the outputs of the AND 39 signal. In the Measurement mode, the switch 40 connects the output of the AND 39 element to the control inputs of the switch 10. When you select the measuring range, a square wave from the output the divider 38 is fed to the control inputs of the switch 10, providing alternate measurement of the voltage on the object and the voltage of the generator, which allows you to measure the object with acceptable accuracy. The division factor of divider 38 depends on the integration time and can not be less than two

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Element And 44 serves to request the passage of pulses to the counting input of the trigger 43 in the Measurement mode.

The debug mode is set by turning on the third switch 41, the third and second switches are switched synchronously). This allows the passage of counting pulses to the trigger input 43 from the output of the 48 state counter and allows parallel recording of information into the division factor 19 and subband 20 counters. Information on the parallel recording inputs (preset inputs) and the subband counter comes from the 48 state counter . The initial state of the counter 48 is determined by the target 51 of the initial code. To organize the cyclic execution of all operations in the measurement (or parts thereof), the target code setting unit 52, the target code comparison circuit 53 and the NAND element are intended.

The forward trigger output 43 through the switch 40 in debug mode is connected to the control input of switchboard 10, and the state of the latter is now dependent on the output signal of the trigger 43. Before measuring in the debug mode, you must set the corresponding value of the setpoint of the upper code and the lower state, the fourth switch 47 is switched so that the output of the second generator 46 rectangular pulses is connected to the counter input 48 of the state 48, and the enable input of the parallel recording of the counter 48 states the fifth switch 43 to connect with the button 50 Start. Pressing the Start button 50 sets the initial state of the 48 state counter, and the second rectangular pulse generator 46 is enabled. Under the action of counting pulses, the state counter 48 enumerates all states from the initial to the final (pre-set by the master codes) thus ensuring the measurement cycle. In debug mode, it is necessary to set the subrange and measurement zone.

The coincidence signal of the comparison circuit 53 prohibits the operation of the generator of 46 rectangular pulses. To re-execute the cycle, you must press the Start button again (figure 5),

Cyclic Hi.iFiojiHemie of the process and:) the measurement is exhausted by switching the fifth switch 49 to its original position after pressing the Start button. In this case, the parallel-write enable signal to the state counter 48 will come from the output of the AU 9 conversion, coinciding with the output of the final state comparison circuit 53.

The step-by-step measurement mode is organized as follows: switches 47 and 49 switch in such a way that their change-over contacts are connected to the output of the Start button. After the first press of the Start button, the switch 49 returns to its initial state. Each subsequent button click

changes the contents of the state counter 48 to one.

Claims (1)

1. An impedance parameter meter containing a voltage source, a measuring circuit consisting of an adjustable model measure, a measurement object and an amplifier, a measuring transducer including: a series-connected synchronous detector and an analog-to-digital converter; a controlled voltage divider, a first switch having a change-over contact connected to the input of a synchronous detector, and two fixed contacts, one of which is connected to the output of a controlled voltage divider and the second, together with the reference input of the synchronous detector and the input of the measuring circuit, is connected to the output of the power source, the controlled frequency divider and the first pulse generator, the output of which is connected to the signal input of the controlled frequency divider, the output of which is connected to the reference input of the analog-digital the converter, the reading device, the first input of which is connected to the first output of the analog-digital converter, the circuit for automatic selection of measurement limits, which includes a divisor ratio counter audio, sub counter, whose output is controlled soedi- nen exemplary action control input and the second input of the even ots- device comparing circuit 0 g p five 0 5 0 5 five rg-rhney and a comparison of the lower boundaries, the first inputs of the KOTopi tx are connected to the analog-digital converter, the upper code setter and the lower boundary code setter, the outputs of which are connected to the second inputs of the upper and lower boundaries, the first element OR, and the element EXCLUSIVE OR, whose inputs are: connected to the outputs of the comparison circuits of the upper ji lower boundaries, the comparison circuit of the upper and the comparison circuit of the lower extreme states of the division counter, the first inputs of which are connected, together with the inputs and controlling the controlled voltage and frequency dividers, with the output of the dividing coefficient counter, the upper code setter and the lower extreme states code setter, output-. which are connected to the second inputs of the upper and lower extreme states comparing circuits, the first and second AND elements, the first inputs of which are connected respectively to the outputs of the upper and lower extreme states comparing circuits, the first inverter whose output is connected to the second input of the second And element and the input together with the second input of the first element AND and the inputs of the reverse of the counters of the division factor and the subdiagonal zones are connected to the output of the first element OR, the second element OR, I / O. The ports of which are connected to the codes of the first and second element AND, the third element OR, the first input of which is connected to the output of the second element OR, the second Ivertor, whose input together with the prohibition input of the counter of the division factor is connected to the output of the third element OR, the fourth element OR whose output connected to the prohibition input of the subband counter, the first input is connected to the output of the second inverter, and the second one is connected to the second input of the third element OR is connected to the output of the EXCLUSIVE OR element, and the clock inputs The dividing factor and subranges coefficients are connected to the output of a voltage source, which is also different from the fact that, in order to simplify the functionality testing and troubleshooting of the device, a second frequency divider, second and third switches, a third inverter, tre7 8 Figg Exit 1 Exit Output Output 9 Output 38 Output 39, fiO Exit 26 Exit gg Exit 21 and R WITH/ g g HU CHU YY  7 H- / Xy .uP / -up 1O - - fch ... (7x limit J g g HU CHU YY  7 H- / Xy (7 BbixodSO Exit 45 flw / oc W j9ft / xorf 5J Exit S r Output / peoffpQ3ih mm ADC and / L hu Ux .J, y v. -p.-v :: jIiiiK.: VV VX GT / L hu: y VV VX 7