SU1583935A1 - Device for multiplying by coefficient - Google Patents

Abstract

The invention relates to digital computing and can be used in the construction of specialized devices. The purpose of the invention is to increase the speed of the device. A new device for multiplying by a coefficient containing a register of 2 coefficients, a block 6 of AND elements, a block 8 of analysis of the sign, a register 10 of the result and a serial adder 11 in the redundant number system is the introduction of the element OR 5 and the parallel adder 9 in the redundant number system, which makes it possible to produce multiplication with a higher speed, independent of the magnitude of the coefficient. 1 il.

Description

6, the second inputs of which are supplied by the 1st Kotor0go are connected to the second input from the value of the bits of the coefficient from the outputs of the register of the 2 coefficients, and to the third - the product sign from the output of the sign analysis block 8, which contains the coefficient sign trigger and the EXCLUSIVE element .OR. To the first inputs of the 1st bit of the parallel adder 9, from the outputs of the 1st pair of elements AND block 6, the values of i-ro discharge of the current product b are displayed, and a k. and its sign b is sign (a1-k,), which are Summed with the value of (il) -ro (minor). The fraction of the partial product from the outputs (il) -ro bit of the result register 10 (z (and. 2 ,, z, and.) In parallel adder 9., the current value of the partial result of the product is generated, which is entered in the result register 10.

the sign analysis unit, the outputs of the higher bits of the result register are connected to the first and second inputs of the first term of the sequential adder in the redundant number system, respectively, characterized in that, in order to improve the device speed, a parallel adder is added in the redundant numeral system and the OR element, the first and second inputs of which are connected respectively to the inputs of the positive and negative values of the multiplicand device, and the output is connected to the third input of the block of elements I, whose outputs with are connected to the inputs of the corresponding bits of the first term of the parallel adder, in the redundant system of the number of which is connected to the second input

the sign analysis unit, the outputs of the higher bits of the result register are connected to the first and second inputs of the first term of the sequential adder in the redundant number system, respectively, characterized in that, in order to improve the device speed, a parallel adder is added in the redundant numeral system and the OR element, the first and second inputs of which are connected respectively to the inputs of the positive and negative values of the multiplicand device, and the output is connected to the third input of the block of elements I, whose outputs with are united with the inputs of the corresponding bits of the first term of the parallel adder, in the redundant system with the number 515839356

The inputs of the bits of the second variable-exact number system, the outputs of which are connected to the outputs of which are connected according to

lower bits of the register with the first and second inputs

with a shift of one bit to the side of the second term sequential

older bits, informational adder in the redundant numbering system which is connected to the output sum. we are parallel adder in huts

Claims (1)

The claims • A device for multiplying by a coefficient containing a coefficient register, a block of AND elements, a sign analysis unit, a result register and a serial adder in an excess number system, the first and second · outputs of which are connected respectively to the outputs of the positive and negative values of the product of the device, the coefficient input which is connected to the information input of the coefficient register, the output of which is connected to the first input of the block of elements AND, the second input of which is disconnected from the output of the block liza of the sign, the first input of which is connected to the sign of the coefficient of the device, the input of negative values of the multiplier which is connected to the second input of the sign analysis unit, the outputs of the highest bits of the result register are connected to the first and second inputs of the first term of the sequential adder in an excess number system, respectively, characterized in that, in order to improve the performance of the device, a parallel adder in the redundant number system and an OR element are introduced into it, the first and second inputs of which are connected respectively, with inputs of positive and negative values of the multiplicable device, and the output with the third input of the block of AND elements, the outputs of which are connected to the inputs of the corresponding bits of the first term of the parallel adder, in an excess number system, the inputs of the bits of the second term of which are connected to the outputs of the lower bits of the register result with a shift by one digit in the direction of the higher digits, the information input of which is connected to the output of the sum of the parallel adder in excess 1583935 ⁶ exact number system, the transfer outputs of which are connected respectively to the first and second inputs of the second term of the sequential adder in the redundant number system.