SU1580533A1 - Linearly varying voltage shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in measuring equipment. The purpose of the invention is to increase the linearity of the output voltage and expand the functionality of the driver. To achieve this goal, a shaper containing a digital-to-analog converter 5, a reversible counter 9 pulses, a trigger 7 characters, switches 3, 4, blocks 15, 16 subtractors, potentiometers 13, 14, a decoder 6, block 10 setting limits, electronic key 18, control trigger 19, switch 8, switches 11, 12, 20, 21. Reversible counter 9 changes its state from "All zeros" to "All ones" and back. Potentiometers 13 and 14 are used to adjust the upper and lower values of the output voltage. Since, for any scale of the output voltage, the number of approximation stages is the same, the nonlinearity is minimal. In the shaper, one-time and cyclic modes of formation of the output voltage are possible, stop at any time, the minimum and maximum values must be set. 1 hp f-ly, 1 ill.

Description

Ulga

20

hf

si

(Xv

about ate

00 SLE

The invention relates to a pulse technique and can be used in measuring equipment.

The purpose of the invention is to increase the linearity of the output voltage and expand the functionality of the driver.

The drawing shows the structural scheme of the proposed shaper.

The shaper contains gain 1, such as FRT pulses, output bus 2, hep and second switches 3 and 4, digital-to-analog converter 5, decoder 6, trigger 7 characters, switch 8, reversible counter 9 pulses, block 10 setting limits, third 11 and fourth 12 turn off. readers, the first 13 and second 14 potentiometers, the first 15 and second 16 rocking units, and the supply voltage bus 17. In addition, the driver contains an electronic switch 18, a control trigger 19, a fifth 20, and a sixth 21 switch.

Bus 1 via electronic switch 18 is connected to the counting input of the reversible counter 9, the output of which is connected to the first input of the second subtracter 16 through the digital-to-analog converter 5, the output of which is connected to the output bus 2. The set and reset inputs of trigger 7 respectively the switches are connected to the common bus and the output is connected to the first control input of the reversing counter 9, the transfer output and the high-level output of which are connected respectively to the first and second inputs of the decoder 6, the first and The outputs of which are connected respectively to the first and second information inputs of block 10, the first and second control inputs of which through the third 11 and fourth 12 switches respectively are connected to the common bus, and the first and second outputs are connected to the second and third reversible counter control inputs respectively 9. The third output of the decoder 6 is connected to the counting input of the trigger 7, the control input of which is connected to the output of the switch 8, the first input of which is connected to the common bus, and the second & stroke is connected to the bus Ecological unit.

The bus 17 is connected to the first terminals of the potentiometers 13 and 14, the second

five

g

0

five

0

five

0

five

0

the pins of which are connected to the common bus and the moving contacts respectively to the first and second inputs of the first block 15, the output of which is connected to the input voltage reference voltage of the digital-to-analog converter 5. The second input of the second block 16 is connected to the second input of the first block 15. The control key input 18 is connected to the trigger output 19, the reset inputs and the settings of which are connected via the fifth and sixth switches to the common bus.

The decoder 6 contains the first and second elements NOT and the first and second elements AND NONE. The inputs of the first and second elements are NOT the first and second inputs of the decoder 6. The outputs of the first and second elements of AND-NOT are the first and second outputs of the decoder 6. The first input of the second element AND-NOT is connected to the input of the first element, whose output is connected to the first input of the first NAND element, the second input of which is connected to the output of the second element NONE, the second input of the second NAND element and the third output of the decoder 6.

Block 10 can be made in the form of two NAND elements, the first inputs of which are information inputs, the second inputs are control inputs, and the outputs are outputs of block 10. Trigger 7 can be made in the form of IK-flip-flops, 1 and The K-inputs of which are combined and are its control input. Switches 3 and 4 can be implemented in the form of P2K buttons with latching, and switches 20 and 21 - in the form of P2K buttons without latching.

For some series of chips used on the R-, S-, I-, K-inputs of the flip-flops, resistors connected to the power supply bus of the microcircuits can be included. In addition, before the specified inputs and inputs of the reversible counter 9 may be included additional inverters.

The shaper works as follows.

When the trigger 19 is set to the state of a logical unit, the electronic key 1b is closed and the clock pulses from the bus 1 passes to the counting input of the reversible counter 9. Changing the contents of the latter leads to an increase or decrease in the output voltage according to a linear law.

ten

5.1580533

In order to ensure the cyclic formation of triangular pulses, the switch 8 is set to a position that ensures the switching of the trigger 7 under the influence of pulses at its counting input. When the reversible counter 9 reaches the state in the subtraction mode, all the zeros, the pulse from its transfer output passes to the third output of the decoder 6, since the output of the high bit of the reversible counter 9 at this moment is a logical zero. The impulse from the first output of the decoder 6, after passing through block 10, confirms the state of All zeroes of the reversible counter 9, and the pulse from the third output of the decoder 6 cuts the trigger 7 by its cut. The following pulses from bus 1 increase the code in the reversible counter 9, which leads to an increase in The output of the digital-to-analog converter 5.

When a reversal score is reached 15

20

Thus, the limits of variation of the output voltage are wide enough and are controlled independently by potentiometers 13 and 14.

In contrast to the known former, in which the reversible counter interrupts the forward and reverse counting with moments of comparing its code with predetermined limits, in the proposed former, the reversible counter 9 is always filled completely, and the voltage difference Uft and U0 affects

Dl

the input voltage of the reference digital-to-analog converter 5. Due to this, the number of approximation stages (i.e., the number of bits involved in the formation of the triangular voltage) always remains maximum. In this case, the nonlinearity coefficient of the output triangular voltage, divided by the formula

specific

K - 4U p

imax

.100%,

By the 9 state of all units, the transfer pulse from its output passes to the second output of the decoder 6 and confirms the state of the reversible counter 9. In addition, this pulse passes to the third output of the decoder 6 and switches the trigger 7. Thus, the formation of the falling portion of linearly begins voltage changing.

Adjusting the voltage change limits at the output of the driver is made by Potentiometers 13 and 14. The output voltages of these potentiometers are fed to the first block 15, the output voltage of which, equal to their difference, affects the input voltage of the digital-to-analog converter 5

35

40

U

 iai

op in (,

In this case, the voltage at the output of the digital-to-analog converter 5 varies from 0 to minus U0 (,.

In the second block 16, the output voltage of the D / A converter 5 is subtracted from the voltage Ujj. The output voltage of the driver is equal to

U

 U

In them, and n Y and varies from Urt when U when U -U rn - (U in - UH)

remains constant for all magnitudes of the output voltage amplitude, i.e. linearity is improved compared to a known former. For JQ receiving a single mode of operation, the switch 8 is set to a position in which the switching of the trigger 7 on the counting input is inhibited. Moreover, after the reversal counter 9 has reached the state All zeros or All units, the transfer pulse from its output passes through the decoder 6 to the second or third control inputs of the reversible counter 9, respectively, confirming the state reached by it. To start changing the output voltage in the other direction, it is necessary to switch the trigger 7 to the opposite state by briefly closing the switches 3 or 4. To force the reversible counter 9 to the extreme states, a short circuit of the switch 11 or 12 is necessary. through the elements of NAND in block 10 to the second or third control inputs of the reversible counter 9, carried out its installation.

Additional functionality is created by connecting the 0 to Ufi key 18, the trigger 19, the switches 20 and 2 |. Short Term 45

50

55

0

0

Thus, the limits of variation of the output voltage are wide enough and are controlled independently by potentiometers 13 and 14.

In contrast to the known former, in which the reversible counter interrupts the forward and reverse counting with moments of comparing its code with predetermined limits, in the proposed former, the reversible counter 9 is always filled completely, and the voltage difference Uft and U0 affects

Dl

the input voltage of the reference digital-to-analog converter 5. Due to this, the number of approximation stages (i.e., the number of bits involved in the formation of the triangular voltage) always remains maximum. In this case, the nonlinearity coefficient of the output triangular voltage, divided by the formula

ode

K - 4U p

imax

.100%,

35

Jq

40

Jq

Jq

45

Jq

50

Jq

55

The switches of switches 20 and 21 allow the trigger 19 to be switched from one state to another and thereby close and open the electronic switch 18 When the latter is opened, the change in the state of the reversible counter 9 and, therefore, the change in the output voltage stops. Using switches 11 and 12 in this mode, it is possible to switch the output voltage from the minimum to the maximum value and back.

Claims (2)

1. A linear variable voltage driver containing serially connected clock pulse bus, reversible pulse counter and digital-analog converter, a character trigger whose output is connected to the first control input of the reversible pulse counter, and the reset and installation inputs are connected via respectively The first and second switches with a common length, characterized in that, in order to increase the linearity of the output voltage, the first and second subtraction blocks, the limit setting block, Rotor, third and fourth switches, switch, first and second potentiometers, the first terminals of which are connected to the supply voltage bus, the second terminals are connected to the common bus, and the terminals of the moving contacts are connected respectively to the first and second inputs of the first subtraction unit, the output of which is connected to the input of the reference voltage of the D / A converter, the output of which is connected to the first input of the second subtraction unit, the second input of which is connected to the second input of the first subtraction unit, and the output to the output bus the transfer output and the high-order output of the reversible pulse counter are connected respectively to the first and second inputs of the decoder, the first and second outputs of which are connected respectively to the first and second information inputs of the limit setting unit, the first and second control inputs of which through the third and fourth, respectively the switches are connected to the common bus, and the first and second outputs are connected respectively to the second and third control inputs of the reversible pulse counter, with the third output the decoder is connected to the counting input of the sign trigger, the control input of which is connected to the output of the switch, the first input of which is connected to the common bus, and the second input to the bus of the logical unit. 2. A shaper according to claim 1, which is based on the fact that, in order to expand its functionality, an electronic key, a control trigger, fifth and sixth switches have been introduced, the electronic key being connected between the clock bus and the counting key. the input of the reversible pulse counter, the control input of the electronic key is connected to the output of the control trigger, the reset inputs and the settings of which are connected via the fifth and sixth switches to the common bus.