SU1577027A2 - Method of controlling adjustable bridge inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control converters incorporated in a variable frequency drive system. The aim of the invention is to improve the spectral composition of the output voltage of the converter in the range of output frequencies close to the nominal. The control method is based on the 180-degree key management algorithm of the three-phase converter with additional valve switchings carried out in the middle of the respective control zones. The associated control of the frequency and magnitude of the output voltage in the lower half of the frequency range is carried out by continuously varying the duration of the pauses between the control pulses and the control pulses themselves in the central sections of the clock intervals of 60 degrees. To reduce the amplitudes of the harmonic components close to the main, in the upper half of the frequency range at intervals of 0-30, 150-180, 180-210, 330-360 e. hail generates additional control pulses, the duration of which increases with increasing frequency, and the locations of the middle of the main control signals are fixed at 75, 105, 255 and 285 e. hail. 5 il.

Description

The invention relates to electrical engineering, to a subclass of power converting technology, can be used in controlling semiconductor frequency converters based on voltage inverters that power asynchronous short-circuited electric motors, and are additional to the invention according to the authors. No. 1492434.

The aim of the invention is to improve the spectral composition of the output voltage of the converter.

FIG. 1 shows the power structure of a three-phase converter, made on the basis of fully controlled keys; in fig. 2 is a timing diagram illustrating the proposed transducer control method; in fig. 3 is a functional diagram of a control system implementing the proposed method; in fig. 4 - time diagrams explaining the algorithm of its work; in fig. 5 - characteristics of the harmonic composition of the output voltage of the converter.

E J

The timing diagrams shown in FIG. 2 illustrates a variant of coupled adjustment of the frequency and magnitude of the output voltage of the converter in the fourfold range (). In the top three timing charts of FIG. 2a shows switching-on control pulses arriving at the initial output frequency at the valves of the cathode group of the converter + L, + B, + C during one half period. The corresponding inverted signals come to the anode group valves. The moments of equality to zero of the cited control signals in the time diagrams correspond to the intervals of the formation of the gate valves of the pulses. In the lower timing diagrams of FIG. Figure 2 shows the corresponding sections of the curve — the inverter output voltage of the converter.

Consider the algorithm for generating valid signals v & t.mgre phase L. At the initial output frequency of the converter F0 (Fig. 2a) in the middle of the conduction zone of the f-A valve, the clock interval is from 60 to 120 e. hail, divided into four segments of equal duration, 15 el. each, inside and in the middle of each of which, control (gate closing) pulses of duration are formed

dgH 1 60 11 25 e-grad At this location of the middle of the control (locking) signals S., and СGO in the first half of the clock interval, calculated as

60 (1 + -t--) are respectively equal

67.5 and 82.5 el. In the second half of the clock intervals, the control pulses are arranged symmetrically throughout the entire control range. At the clock interval from 240 to 300 e. Grado in the zone of the closed state, the valves in the same way produce signals for switching on the valve.

Frequency control of the output signal of the converter at the considered control algorithm in the range

N frequency band FQ-xF is carried out in

an account of the constant stepwise variation of the lengths of the central ones in the clock intervals of the control pulses and the durations of the pauses between the main pulses in the central parts of the clock intervals of 60-degree durations. On the control subbands where the duration of the remaining control signals does not depend on the current values of the output frequency of the converter and is determined by the duration of the control pulses in the central clock intervals.

from the relation A zy | 72t-TT where the number of control signals generated at half the clock intervals, including the central one. On the control subbands, on which the control is carried out by varying the duration of the central pauses between the main control pulses, the duration of the remaining control signals varies depending on the current values of the transducer's output frequency in accordance with the functional dependence of dt m (- -

12. i F F0 Ы

After the output frequency of the converter reaches F0 and up to the nominal frequency, the described algorithm for generating control signals is modified.

All of the above dependences relate to the duration of the control signals that cause the valves to be locked within the 180-degree zones of the open state of the keys and the activation of the corresponding valves inside the closed-state zones, the time intervals equal to the duration of the said signals.

In the analyzed variant of the associated four-frequency adjustment of the converter () on the first control sub-band, the change in frequency (period duration) is performed by varying the duration of the control pulses in accordance with the dependence

  - -U-Lfi - -C

L 12iV F0N; 4F / and with the current location of the control pulse centers

(2 |: 1) bo (i-§ | -) el.grad ,. C eOO + f- 2.2-1) ELAgrad

The first in order regulation range is occupied by the frequency range.

V..zi r-ir $ & Јtt rs

1,09F0,

whereupon, the control pulses closest to the middle of the clock intervals merge into one central control signal of an increased duration.

The control subrange of the converter located in the zone of output frequencies FЈ - F. „

F 2 (2H7 (272-T) + T 171 Fa xaPaKTePH is the presence of central control signals located in the middle of the clock intervals, the length of which varies from frequency in accordance with the dependence ./1 2i-1) (21H) + 1M 6F 6FeN (2i-t) 6F 2 () (212-1) +1 1 7 6-4 (2r2 -17g 6F 72F /

The duration of the main remaining control signals, while remaining

i-1 constant and equal to A

2H 1 (2-2-TTF

Increasing the output frequency of the transducer from F 2 to the output frequency equal to half the commemorative F N

rF 2F, is accompanied by a gradual decrease in the duration of L of control signals according to (зависимости; - 7Ј) characteristic characteristic of 12 i 41 a

A feature of the proposed converter control method is the modification of the control algorithm in the range of elevated output values

NFn frequencies - NFj. So, starting with the toTbi F clock

The control signal dyne is firmly actuated at 75,105,255 and 285 e. hail. At the same time at intervals of 0-30 150-180, 180-210 and 330-360 el.grad. generate additional control pulses, one at each of the specified intervals, the duration of which is from the function

o

five

0

five

0

five

0

five

the dependence of t (-fn- - 5.78)

2 89F NFe

  5.78) el .. Nearest to

about

to the half-period boundaries, the fronts of the additional control signals in this case are formed by shifting by ± 60 electrical degrees. Near to the middle of the half-periods of the edges of the corresponding corresponding (switching on or off) main control signals. The indicated subband operation of the converter is illustrated by the time diagrams presented in Fig. 2, b.

Duration of additional control signals on the range

NF0., „

-x- -NFe increases linearly

from close to zero, with often NFo those -r- up to 5.78 el.grad., observable

at the nominal output frequency of the NF0 converter. In the linear output voltage curve, as shown in FIG. 26, additional output pulses are formed at the edges of the half-periods on the marked control range, which contribute to the reduction (compensation) of the amplitude of the parasitic harmonics of the spectrum, close to the main harmonic.

The principle of building control systems that implement the proposed method will be considered on the example of a control system, the functional diagram of which, corresponding to the variant, is shown in FIG. 3. Block 1 specifies the output frequency of the converter, the analog signal generated at the output of which is directly proportional to the output frequency and determines the frequency of the clock of the generator of 2 clock pulses, which is 12 times higher than the output frequency of the converter, is also connected to the plus input of the adder 3 The output of the generator 2 is connected to the inputs of the register 4 and the generator 5 of the sweeping linearly varying voltage, the output signal of which has a constant to both sides in the whole range of operation and a variable amplitude decreasing with increasing frequency, which is detected by amplitude sensor 6. The output of the generator 5 is connected to the inputs of the comparators 7-11, in which the signal of the Uj-generator 5 is mapped to the output voltages of the adders

71577027

12-46. The output of sensor 6 is also connected to the positive input of the adder 17.

The operation algorithm of the device, made according to the vertical principle, is explained by the timing diagrams presented in FIG. 4. In this case, the indexes of the signals in FIG. A correspond to the numerical designations of the corresponding blocks and nodes in the functional diagram of the device. The amplitudes of the signals from sources 18 and 19 of a constant voltage determine the temporal positions of the midpoints of the pulses of the output voltage curve of the converter at the initial output frequency. At the same time for Uw Chu / ike

eight

the fronts of the output pulses, which through the OR 24 element arrive at the input of the counting trigger 25 and further, at the input of the logic distributor 26 of control pulses.

The described basic algorithm of the device operation takes place on the lower frequency range of the transform 10

tel

When the output frequency of the converter reaches the specified amplitude limit value of the signals U, g of the source 19 and U

UfeeO, 5U, MeKC, where u5 / iax is the maximum amplitude of the sawtooth signal of generator 5, is observed at the key of the key 29. A further increase

6 at the output of sensor 6 becomes equal, which leads to the triggering of the comparator 27, switching from one position to another at the command of the comparator 27 key 28 and

output frequency. Sources 1S and 19 are connected to the r by the nasal inputs of the adders 13–16, and to the other inputs, the signal is received from a source 10S source whose amplitude is the initial 15 duration of the output pulses.

U40, 0625 and M0i. On

The inputs of the adders 13-16 also come in a correction difference signal from the output of the adder 21, which is zero at the frequency, due to which the total duration of the output pulses, whose temporal position is determined by the amplitudes of the signals at the outputs of the adders 13-16, in the process of regulating the converter remains constant This corresponds to the law of the constant ratio of the magnitude of the voltage to the frequency. The magnitude of the Q voltage U of the reference source 22 is determined from the ratio

-tt-SJiUSfrsn 9chp ia N and um 5 with 45

From this signal, the adder 21 subtracts the signal of the resulting adder 23, the positive inputs

35

U.

The output frequency of the converter, up to the nominal output frequency 4F0, occurs when the temporal position of the mid-pauses between the output pulses, which is shown in FIG. 4 with respect to the control signals of the + A phase valve are designated C and C. At the same time, a positive difference signal from the output of the adder 3 (it is considered that the maximum amplitude of the output signal of the block) Kc) is through the matching amplifier 30 to the input of the adder 12, where it is summed with the voltage i. The total signal U. through the key 29 arrives at the input of the comparator 7 with the driver of short pulses at the output, generating command pulses at the moments of equality of the signals Uj and U, which, through the element OR L, to another input, which comes pulses from the comparator 10, arrive at the input of the counting trigger 32 and cause its periodic operation. The positive input of the adder 23 receives a signal through the switch 33, controlled by the comparator 34. The signals at the outputs of the counting triggers 25 and 32, indicated in FIG. 4, the output frequency of the converter, up to the nominal output frequency 4F0, occurs when the temporal position of the mid-pauses between the output pulses, which is shown in FIG. 4 for the control signals, the phase + A valves are designated C and C. At the same time, a positive difference signal from the output of the adder 3 (it is considered that the maximum amplitude of the output signal of the block) Kc) is through the matching amplifier 30 to the input of the adder 12, where it is summed with the voltage i. The total signal U. through the key 29 arrives at the input of the comparator 7 with the driver of short pulses at the output, generating command pulses at the moments of equality of the signals Uj and U, which through the element OR L to the other input, which comes pulses from the comparator 10, arrive to the input of the counting trigger 32 and cause its periodic operation. The positive input of the adder 23 receives a signal through the switch 33, controlled by the comparator 34. The signals at the outputs of the counting triggers 25 and 32, indicated in FIG. 4 correspondences of which are connected with the outputs of adders 14, 16 and 17, and the minus input JQ is validly as 131, the adder 23 is connected to the output of the sum to the inputs of the logical distributor 26 of the mat 15. Thus, the signal size

control pulses. The clock inputs of the distributor 26 receive signals of the four-bit register 4, the output states Q., 0, Q3.0. which digitally over the period of the output voltage can be sequentially recorded as 1000, 1001, 0010, 0011, 0000, 0001, 1010, 1011, 1100, 1101,

U ,,. is proportional to the total duration of output pulses over a half period. At the moments of the equality of the signals U 1a -U 6 to the current values of the sweep voltage U5, the comparators 8-11 produce short im (commands) to form

eight

the fronts of the output pulses, which through the OR 24 element arrive at the input of the counting trigger 25 and further, at the input of the logic distributor 26 of control pulses.

The described basic algorithm of the device operation takes place on the lower frequency range of the transform 10

tel

When the output frequency of the converter reaches the specified amplitude limit value of the signals U, g of the source 19 and U

kaniyu key 29. Further increase

6 at the output of sensor 6 becomes equal, which leads to the triggering of the comparator 27, switching from one position to another at the command of the comparator 27 key 28 and closing the key 29. A further increase

The output frequency of the converter, up to the nominal output frequency 4F0, occurs when the temporal position of the mid-pauses between the output pulses, which is shown in FIG. 4 for the control signals, the phase + A valves are designated C and C. At the same time, a positive difference signal from the output of the adder 3 (it is considered that the maximum amplitude of the output signal of the block) Kc) is through the matching amplifier 30 to the input of the adder 12, where it is summed with the voltage i. The total signal U. through the key 29 arrives at the input of the comparator 7 with the driver of short pulses at the output, generating command pulses at the moments of equality of the signals Uj and U, which through the element OR L to the other input, which comes pulses from the comparator 10, arrive to the input of the counting trigger 32 and cause its periodic operation. The positive input of the adder 23 receives a signal through the switch 33, controlled by the comparator 34. The signals at the outputs of the counting triggers 25 and 32, indicated in FIG. 4 respectively as well as 131, are fed to the inputs of the logical distributor 26

Q is valid as 131, go to the inputs of the logical distributor 26

control pulses. The clock inputs of the distributor 26 receive signals of the four-bit register 4, the output states Q., 0, Q3.0. which digitally over the period of the output voltage can be sequentially recorded as 1000, 1001, 0010, 0011, 0000, 0001, 1010, 1011, 1100, 1101,

1110, 1111. In this case, the logical functions implemented by the distributor 26 and arriving in the form of enabling control signals to the corresponding valves are of the following form

 2A Mg “U3a + Q / Mzi“ + + QiQr (b (Uu3i + Q, QtQ3Q4U: + Q7Q, tQЈ i5 + QtQ Q4 + Q Q bQ4U34;

+ B-Q1Q, Q3U15 + Q, Q1QSQ4U3 +

+ Q1M3Q4U3a + M7Q3Q + Q.TQiQ3ul5 + + QfQ2Q3Q Q, qiQ3Q4uM + q1QlQ3Q4u35;

+ C QfQЈ30 Q.q, 1Qiq4U3a +

QtQ3Q4u3 "+ Q, Q4Q3u" + QiQiQЈ4u9t +

+ QiQiQ3Q4U3i + Q, QaQsQ4 + Q, Q2Q3Ulf.

Formation in the upper frequency range of the converter operation of additional control signals with linearly varying from the continuation frequency 30

This leads to the appearance on the extreme parts of the linear output voltage curve of additional pulses of the same duration, providing compensation for the amplitudes of the parasitic harmonic components of the spectrum that are close to the main one. This is illustrated in the figure shown in FIG. 5, calculated for the variant, the dependence curves of the relative, reduced to the voltage of the power source E, the amplitudes of the fifth and seventh harmonics for the proposed (solid lines) and known (dashed curves) methods. With this selected

ten

f5

„0

 , the law of changing the duration ji, at which at FaNF0 5.78 electr., provides at the nominal frequency full compensation of the fifth harmonic, the amplitude of the seventh harmonic in the upper part of the control range is also quite small and does not exceed a few percent of the main one.

Claims (1)

Invention Formula A control method of an adjustable bridge inverter with N-fold coupled frequency control and a half-period average value of the output voltage of the auth.w. IP 1492434, characterized in that, in order to improve the spectral composition of the output voltage of the converter in the range of output hours N that -F -NF, the location of the means The main valve off and on signals are defined respectively as 75,105,255 and 285 el.grad, and at intervals of 0-30, 150-180, 180-210 and 330-360 el.grad. they form additional shut-off signals and on-off valves, the fronts closest to the boundaries of the half-periods of which are formed by shifting 1bO zl.grad. Near to the middle of the half-periods of the front of the corresponding main valve off and on signals of the same name, the duration of the additional valve off and on signals is determined from the functional distance 35 40 dependencies at (- Ј 5.78) el.grad.  NE, -t- M I r i Jl + A +8 + C I L -A I © 38s §0 ° As SO P, P, m .m ff ° r five lllllgii 0s / .. 60 ° yes  five 55 a m rn A 0 ".2 -eight X qr -Ј z  A lze c .fa.1 / 20 ° 180  50 ° h 1- LT Submarine Fff