SU1555919A1 - Device for monitoring multichannel analog-digit conversion of image signals - Google Patents

Abstract

The invention relates to television technology and can be used in test and measurement systems for various purposes. The purpose of the invention is to expand the functionality by simultaneously monitoring all N bits of the M-channel ADC. In order to ensure control of multi-channel, multi-bit ADCs, a divider of 16 horizontal frequency by the number N and the number 3N, channel elements AND 7–9, counters 26–28 N pulses, and bit elements AND 29–31 are entered into the device. An accurate quantitative estimate of the x-ki quantization error is carried out by combining the vertical risks intersecting all bits of the code with the boundaries of the change in the glow of the bands of the corresponding code bits. The use of the device allows for the on-line monitoring and adjustment of both single-channel and multi-channel multi-bit ADCs, as well as quality control of their operation using the comparison method, which significantly reduces the time required for monitoring and setting up the equipment, simplifies and facilitates the operator’s work. 1 il.

Description

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control of all N bits of M-channel ADC. In order to ensure control of multi-channel, multi-bit ADCs, a 16 line frequency divider for the number N and the number 3N, channel elements AND, counters 26-28 N pulses, bit elements AND the Control of the quality of the ADC or accurate quantitative error estimate x are entered into the device. - quantization is done by combining vertical risks that intersect the whole invention. The invention relates to television technology, in particular to the control of analog-to-digital converters (ADC), and can be used in instrumentation systems. various purposes.

The purpose of the invention is to expand the functionality by simultaneously monitoring all N bits of an M-channel analog-digital converter.

The drawing shows a block diagram of a device for monitoring a multi-channel analog-digital image signal converter for a variant of monitoring a three-channel () A / D converter having N bits in each channel.

The device contains a three-channel ADC 1, which includes the first 1.1, the second 1.2 and the third 1.3 single-channel ADC, the generator 2 test signals, which contains the generator 3 sawtooth voltage, the generator k half-frame clock pulses, the generator 5 horizontal clock pulses, video monitoring unit (WKB) 6 The first 7, the second 8 and the third 9 channel elements AND, a three-bit register. 10 shifts, first 11 and second 12 delay lines, first 13 and second 1 differentiating units, prohibition block 15, horizontal frequency divider 16 by number N and 3N, element OR 17, reference voltage source 18, measurement unit 19, comparator 20 tags, differentiator block 21 of the comparator, limiter 21, first 23, second 2k and third 25 multiplexers, first 26, second 27 and third 2.8 counters N pulses, first 29, second codes, with boundaries for changing the bands of the corresponding bits code. The use of the device allows for the on-line monitoring and adjustment of both single-channel and multi-channel multi-bit ADCs, as well as quality control of their operation using the comparison method, which significantly reduces the time required for monitoring and setting up the equipment, simplifies and facilitates the operator’s work. 1 il.

a swarm of 30 and a third 31 bit elements I.

The control device of the multi-channel analog-digital image signal converter works as follows.

The signal from the frequency divider 16 arriving at the inputs of counters 2.6-28 in the form of bursts of pulses gated using elements AND pulses from the outputs of the shift register 10 controls the flow of information from the outputs of the ADC bits through multiplexers to the elements AND to the other inputs of which the same pulses from the outputs of the shift register 10, and after summing up on the element OR 17, are supplied to the VCB 6 for display on the screen. The signal from the output of the half-frame sync-pulse generator sets the counters 26-28 to the initial state, and also enters the shift register 10, which generates gating pulses using signals from the output of the 16 frequency divider. The bit information from the outputs of the ADC is the digital equivalent of the sawtooth voltage coming from the output i of the generator 3 sawtooth, voltage. In order to accurately quantify the error of the quantization characteristic, a narrow vertical risk is formed on the screen of the WKB 6, intersecting all bits of the code. The moment of occurrence of the signal risks corresponds to the instantaneous value of the sawtooth signal, equal to the voltage at the output of the source 18 of the reference voltage. The limits of adjustment of the source 18 of the reference voltage must be no less than dynamic

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range of the investigated ADC. Measurement block 19 is used to measure the reference voltage to be set. Using the comparator 0 mark, the current value of the sawtooth voltage is compared with the reference voltage. The voltage drop at the output of the 2D marker comparator, which is formed at the time of matching the current value of the sawtooth signal and the reference voltage, is converted by means of differentiating unit 21 into a narrow pulse, forming an element of risks, a incoming limiter 22 into an element OR 17.

In order to measure the real quantization characteristic, it is necessary to consistently combine the measurement risk with the limits of the change in luminosity of the corresponding bit of the ADC code and fix it with the help of the voltage measurement unit 19 at the time of combining.

The device allows to obtain on the screen of the OKB 6 real quantization characteristics of analog-digital converters, the number of which is determined only by the necessary minimum of lines for each bit of the ADC, which does not cause rapid visual fatigue, as well as a resolution of 8KB 6, and a quantitative estimate of the conversion error is determined by the accuracy of the block used. The 19-real characteristic on the screen of the VCB 6 is displayed in the form of code tables consisting of horizontal bars of variable luminescence, the number of oryh corresponds to the total number of bits of the connected code ADC. In each of the bits, the logical O corresponds to the level of black light. The vertical width of the bit stripes depends on the number of lines forming the strip, which is determined by the division factor of the frequency divider.

The use of the proposed device allows for the operational monitoring and tuning of both one channel and multichannel multi-bit ADCs, as well as the quality control of their operation by the comparison method, which significantly reduces the time required for monitoring and setting up the equipment, simplifies and simplifies operator labor.

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Claims (1)

Invention Formula A multichannel, analog-to-digital image signal converter control device, comprising a test signal generator, consisting of a sawtooth voltage generator, the output of which is connected to the input of a multichannel analog-digital converter, consisting of M combined at the input of an M-digit single-channel analog-to-digital converters, a semi-frame sync pulse generator and a horizontal sync pulse generator, a video monitoring unit whose external synchronization inputs are connected to the output home of the half-frame sync pulse generator and with the output of the horizontal sync pulse generator, the reference voltage source, the output of which is connected to the input of the measuring unit and the first input of the label comparator, the second input of the comparator of the label and the output of the sawtooth voltage generator, and the output is connected to the input of the comparator differential unit tags whose output through the limiter is connected to the control input of the OR element, the output of the OR element is connected to the video signal input of the video monitoring unit, M-bit day The shift register, whose information input is connected to the output of the generator of half-frame clock pulses through the first differentiating unit connected in series and the first delay line, whose input is combined with the input of the second delay line, the output of the generator of half-frame clock pulses, the control input of which is connected to the second differentiating unit, to the combined control input of the M-bit shift register, characterized in that, in order to expand the functionality of the By the simultaneous control of all N bits of an M-channel analog-to-digital converter, which has N-M ЈN, where M; - the number of active lines in the TV half-frame, the horizontal frequency divider by the number N and the number MN, whose information input is connected to the output of the horizontal sync pulse generator, is entered, the division number by Ш is connected to the input of the second differentiating unit 71 strobing outputs of the horizontal frequency divider are cured to the output of the second delay line, the first, second, ..., M-th bit elements AND, the first inputs of which are combined and connected to the output of division by the number N of the horizontal frequency divider, and the second inputs are alternately connected to the same-name bit outputs of the M-bit shift register, first, second M-th channel elements And, the first inputs of which are combined with the second inputs of the same-named bit elements AND, and the INPUTS are connected to the same-named inputs of the OR element, first, second, ..., Mth counters N pulses, the control inputs of which are combined and connected to the output generator floor 0 five eight frame sync pulses, counting inputs are alternately connected to the outputs of the same-named bit elements AND, and the bit outputs of the first, second, ..., Mth counter N pulses are connected to the address inputs of the first, second, ..., Mth multiplexer, respectively The first, second, ..., Nth signal inputs of which are connected to the first, second, ..., Nth bit outputs, respectively, of the first, second, ..., Mth single-channel analog-to-digital converter, the outputs of the first, second, ..., M th multiplexer are connected to the first inputs of the corresponding about the first, second, ...., Mth channel element AND,