SU1552185A1 - Test shaper - Google Patents

Abstract

The invention relates to automation and computing and can be used in control devices. The purpose of the invention is to increase speed. The shaper contains the test output unit 4, the pseudo-random code generator 1, the control unit 5, the microtest sequence generating unit 2 6, and the decoder 3. 7 ill.

Description

t

(L

m

5 ± 2

AND

The invention relates to automation and computing and can be used in control devices.

The purpose of the invention is to increase speed.

Figure 1 shows the structural phhema forcing; figure 2 - diagram of the pseudo-random code generator; FIG. 3 is a block diagram of the formation of the Microtest Sequence; on сrig.4 - diagram of the test delivery unit; Fig. 5 shows a block diagram of the operation of the control unit; Fig. 6 is a diagram of the control unit; . on Fig.7 - timing charts of the shaper.

The test driver contains the generator of 1 pseudo-random codes, the JZ sequence generation block JZ, the decoder 3 co-manda length, the test output node 4, the control block 5.

In the generator (Fig. 2), a shift register 6 and a modulator two adder 7 are used.

Block 2 (FIG. 3) contains a pseudo-random sequence generator 8, a register 9, a block of 10 memory of a modified matrix of transient probabilities, and a block of 11 a memory of command codes

The test output node 4 (FIG. 4) is pre-assigned to form the next {command word and consists of a multiplexer 12, a buffer register 13, a trigger 14, an OR element 15, and a delay element 16.

Control unit 5 (Fig. 5) is a synchronous control unit. an automaton with multiple internal states | aD, a1, .. ,, a7JH contains a generator of 17 clock pulses, elements AND-OR 18 and 19, elements AND 20-29, elements OR 30-34, and triggers 35-37. Moreover, the elements 18-21, 30 form the decoder, the elements 22-29 and 31-34 form the encoder.

Pseudo-random code generator 1 is designed to generate random numbers used as second, third, etc. command words, i.e. as addresses and data In the simplest case, it can be implemented on shift registers with feedback.

The microtest sequence forming unit 2 is designed to form the first word of a command. Formed words form

0

five

0

five

0

five

0

five

0

five

 a pseudo-random sequence in which the probability of the occurrence of the next command code depends on which command code was issued in the previous cycle. The stochastic properties of this sequence are determined by the transition matrix of the Markov chain.

The decoder 3 is designed to determine the structure of the generated command. The first word of the command arrives at the input of the decoder, and the signal of the logical unit appears at its i-th output, where i is the length of the command to be decoded. The decoder has outputs 1-1, where 1 - the maximum possible length of the command).

The pseudo-random number generator 8 generates uniformly distributed numbers. In the simplest case, it can be implemented in the same way as generator 1 (FIG. 2). When a signal is applied to the generator 8 start, a pseudo-random number appears at its output. The next pseudo-random number is generated when the next start signal is applied, etc.

Register 9 is for storing the current status number (row address) of a Markov chain. Block 10 of the memory of the modified transition probabilities matrix is a two-dimensional array of log2nL-bit words, where n is the number of Markov circuit states. The number n of circuit states is determined by the number of microprocessor commands for which the corresponding test is to be formed. Addressing This is done by specifying the row number in register 9 (input A) and the column number at the output of generator 8 (input Hell). The number of rows of block 10 of the memory of the modified transition probabilities matrix is n, and the number of columns is 2, where m is determined by the method of representing the transition probabilities

- g /. , about ; .

-; ji, d, j

whole,

 in the form of Pu

In the simplest case, block 10 and block 11 are permanent storage devices containing the corresponding matrix and codes. The multiplexer 12, depending on the value of the signal on its control input, transmits to the output either data from input D (, (Q 0), or data from input D h (Q 1). In more complex cases

when forming tests for different types of microprocessors blocks

10 can be implemented in the form of re-p programmable memory devices or random access memory devices. When using random access memory devices, before starting up the shaper in blocks 10 and

11, the corresponding matrix and necessary codes are loaded (in FIG. 3, loading devices are not shown).

Elements 18-21 and 30 implement the excitation function of the automaton memory, triggers 35-37 automaton memory, elements 22-29 form the automaton state decoder, elements 31-34 form the output encoder.

The transition table of the automaton implements the control algorithm shown in Fig. 5, where the X symbol indicates the memory states of the automaton. In this case, the states are encoded as follows: a 0 - 000; a - 010; aa- 11 ai- 110; a 4 - 100; as - 101; a6 - 001; a - 011, where, by binary numbers of the form, tf Q c / e, the states of the triggers 37, 36 and 35 are indicated.

Shaper works as follows. /

In the initial state, the triggers 35-37 and the register 9 are set to the zero state (the initial installation circuits are not shown). If blocks 10 and 11 are made in the form of random access memory, before starting work, block 10 is loaded with a modified matrix of transient probabilities A, and in block 11 — codes of the commands to be checked (in FIG., 3 loading devices are not shown). A modified transition matrix A is obtained as follows.

The pseudo-random sequence of test commands that must be worked out at the input of the driver is considered as a Markov process defined by a simple homogeneous Markov chain of the form S i 0, p-1, with a transition matrix

probabilities P || R; | the probability of transition in one state S, to that state for each state S-,

gde shch

P tact out

SK. In the case of a Markov circuit, some instruction Ij of the microprocessor under test corresponds. Sequences of states through

which passes the chain of Markov, corresponds to the sequence of commands issued at the output of the driver. The transition probabilities PiK are chosen based on the requirements of ensuring loading conditions, occurrence and transportation of faults.

Imagine each element of P, as

 to

U

 tf

Ik

15

0

five

0

35

0

five

0

five

where CS /; K is an integer, m is an integer.

The value m determines the accuracy of the representation of the elements of the matrix P. The modified matrix of transition probabilities A has the form A || .

1 0, n-1, j 0 ,. The string Aif corresponding to the state S is a numerical sequence consisting of n series, and the K-series corresponding to the state 5c consists of the numbers k, repeated / -, times.

Thus, each line A | contains the numbers of all possible next states SQ, S t, ..., Sc, ... S (i - | 7 and the number of repetitions of each number k of the state S K is directly proportional to the probability P; K.

When using permanent or reprogrammable memories, blocks 10 and 11 contain a modified matrix A and the corresponding command codes.

The signal generator start 17 clock pulses begins the formation of clock pulses.

Since the triggers 35-37 are in the zero state, the first clock pulse through the elements 22 and 31 is fed to the input of the Start-up of the block 2. At the same time, the generator 8 produces a pseudo-random number. On the trailing edge of the first clock pulse, the trigger 36 goes into one state.

The second clock pulse through the elements 23, 32 and 33 enters the block

2 and input Start generator 1 pseudorandom codes. This reads from block 10, and the pseudo-random code generator 1 generates a pseudo-random number. The address of the string is the contents of register 9, i.e. zero,

and the pseudo-random number received from generator 8 is used as the column address. At the output D of the memory block 10 of the modified matrix of transition probabilities, the number k of some state S «of the Markov chain appears, i.e. the circuit goes from state S to state S. On the trailing edge of the second clock pulse, the flip-flops 35 and 37 go to one state (state qt) of the controlling automaton).

The third clock pulse through the elements 24 and 31 is sent to the Start and Receive inputs of the command code generation unit 2. In this case, the generator 8 generates the next pseudo-random number, and the state number S from the output of the memory block 10 of the modified transient probabilities matrix is stored in register 9. At the same time, the process of reading from the code memory 11 of the instruction codes is started, at the output D of which the IK command code appears corresponding to the state S $. The command code 1 goes to node 4 and to the decoder 3 the length of the command. On a specified front of the third clock pulse, the trigger 35 goes to zero state.

The fourth clock pulse through the elements 25 and 32 is fed to the input of the Reading unit 2 forming the sequence of command codes and to the Input 2 of the test output unit 4. This starts the reading process of the memory block 10 of the modified transition probabilities matrix, i.e. in the Markov chain, a transition is made from the state SK to some other state S :. Simultaneously trigJ

The ger 14 of the node 4 is set to one, switching the input DS of the multiplexer 12 to its output. The considered clock pulse, the transition through the OR 15 element and the delay element 16, fixes in register 13 the 1K command code received from the output of block 2. On the falling edge of the fourth clock pulse, depending on the value of the signal at the output 3.1 of the decoder, the command length 3 occurs following:

if the command length is one, output 3.1 is in one state and trigger 35 is set to one;

5 0 5 0

50

5 Q

five

otherwise, the flip-flop 36 is reset (state 04 of the control automaton).

In case the length of command I is equal to one, then the next clock pulse returns to inputs Receipt and Start of block 2 in register 9 is fixed number j of state S, command I of code 11 is read from command block memory 11: On the trailing edge of the considered the clock pulse is reset by the trigger 35. The next clock pulse arrives at the input 2 of node 4 and the input of block 2. The register Ij of the following command is recorded in register 13, and the block of memory of the modified transient probabilities is initiated in memory 10 present state of the Markov chain.

If the 1K command has a length of more than one, then the next clock pulse through elements 26 and 34 goes to Input 1 of node 4, sets trigger 14 to the cool state, connects input D of multiplexer 12 to its output and fixes to register 13 as the second command word code from the output of the generator 1 pseudo-random codes. On the trailing edge of the clock pulse, the trigger 35 is set to one.

The next clock pulse through the elements 27 and 33 is fed to the input of the Start of the generator of pseudo-random codes, which generates the next pseudo-random number. On the falling edge of the clock pulse, depending on the value of the signal at the output 3.2 of the decoder 3, the following occurs:

if the command 1K length is two, output 3.2 is in the one state and trigger 36 is set to one.

otherwise, the trigger 37 is reset.

In the event that the length of command I is equal to two, with the arrival of the next clock pulses, the next command code is generated in a similar way.

If the length of a 1K command is more than two clock pulses through elements 28 and 34, 15 and 16 fixes in register 13 the third command word received via multiplexer 12 from the generator

1 pseudo-random codes. On the trailing edge of the clock pulse, the trigger 36 is set to one.

The next clock pulse through the elements 29 and 33 is fed to the input of the Start of the generator 1 pseudo-random codes, which produces the next pseudo-random number. On the trailing edge of the clock pulse, the trigger 37 is set to one. With the arrival of the next clock pulse, the formation of the next command code begins.

Claims (1)

Invention Formula A test driver containing a test output node, a pseudo-random code generator, a control unit, the output group of the test delivery unit is a output generator group, the control unit contains two decoders and a trigger group, the first output group of the first decoder is connected to an input group the settings of the corresponding group triggers, the test output node contains a buffer register, a multiplexer, a trigger, an OR element, a multiplexer output. connected to the information inputs of the buffer register, the output group of which is connected to the output group of the test output node, characterized in that, in order to improve speed, the driver contains a microtest sequence forming unit, the test issue node contains a delay element, the control unit contains a third decoder and a clock generator pulses, the microtest sequence forming unit contains two memory blocks, a pseudo-random sequence generator, a register, and the first output is The control unit decoder is connected to the reset input of the trigger of the test output node and the first input of the test output node OR, whose output through the delay element of the test output node is connected to the synchronization input of the buffer register of the test output node, the second output of the second decoder of the control unit the test output node, the second input of the OR element of the test delivery node, the trigger output of the test output node is connected to the control input of the multiplexer of the test delivery node of the first information group x inputs of which are connected to a group of outputs of a pseudo-random code generator whose synchronization input is connected to a third output of a second decoder of a control unit, the fourth output of which is connected to the start input of a pseudo-random sequence generator of a sequence generating unit of microtests; micro tests, the group of outputs of which is connected to the group of information inputs of the register and with the group the address inputs of the second memory block of the microtest sequence forming unit, the output group of which is connected to the group of information inputs of the third decoder of the control unit and the second group of information inputs of the multiplexer of the test delivery unit, the fifth output of the second decoder of the control unit of the microtest sequence generation and permission entry the second memory block of the microtest sequence forming unit; the sixth output of the second decoder of the control unit is connected to the enable input of the first memory block of the microtest sequence forming unit, the second group of address inputs of which is connected to the output register group of the forming unit microtest code sequences of a group of outputs of the third decoder of the control unit connected to the first group of information inputs of the first decoder of the control unit, the second group of information inputs of which are connected to the first group of outputs of the second decoder of the control unit whose output is connected with the reset input of the first trigger i control unit groups, inputs resetting group triggers, excluding the first trigger, is connected to the second group of outputs of the first decoder of the control unit; the gate input of the second decoder of the control unit is connected to the output of the clock generator of the control unit and to the trigger synchronization inputs control unit groups, the output group of which is connected to the group of information inputs of the decoder R Oty Squeak  WITH D v I control unit, the start input of the clock pulse generator is connected to the start input of the driver. " Fah.g WITH  block2 jf7 Read on unit 2 Start on generator 1 Acceptance. Start on block 2 Input2 to the node H Read to block 2 Ad ffxod / node 4 Start on generation 1 Da clin Teams-2 No willows 1 Logon, node 4  general Start ) iSL JLЈL 5 u u arv to 5.} k5ts H / rf to 5.5 Schr Phk ts Faye. 6 K5t KS.Z to 5.} nJOJlJUULJlJUUUUUUUUUl. A l L : t Lp --t. Ltl  t t t t Ltl P Tl