SU1545218A1 - Device for extraction of square root and its reciorocal - Google Patents

Abstract

The invention relates to computing and can be used for hardware computation of the square root and its reciprocal in the redundant number system in fixed-point form. The aim of the invention is to improve the speed of the device. The device allows us to process data as it arrives and simultaneously correct the results obtained after each iteration. 1 il.

Description

one

(21) 4417074 / 24-24

(22) 04/18/88 (46) Feb 23, 90. Bul № 7

(71) Kiev Institute of Civil Aviation Engineers. 60 years of the USSR

(72) I.A. Zhukov, L.Ya. Nagorny (SU), Dai Singh (IN) and Joseph Behenduz (W.)

(53) 681.323 (088.8)

(56) USSR author's certificate

fr 732863, cl. G 06 F 7/552, 1978.

USSR author's certificate number 1024914, cl. G 06 F 7/552, 1983.

(54) DEVICE FOR EXTRACTING SQUARE CDRN and HIS RETURN VALUE

(57) The invention relates to computing and can be used for hardware calculation of the square root and its reciprocal in the redundant number system in fixed-point form. The aim of the invention is to improve the speed of the device. The device allows us to process data as it arrives and simultaneously correct the results obtained after each iteration. 1 il.

The invention relates to computing and can be used for hardware calculation of the square root and its reciprocal.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of the device.

The device consists of iteration calculation blocks 1, correction blocks 2, device synchronization 3-8, input 9 logical zero, information inputs 10 and 11 of the device; iteration calculation I blocks contain registers 12 and 13, adders 14 and 15, registers 16 and 17 shear, difference analysis block 18; Correction blocks 2 contain registers 19 and 20, subtracters

21 and 22, shift registers 23 and 24, difference analysis block 25, switches 26 and 27, information outputs 28 and 29 of the device.

The calculation of the square root and its inverse is made using an algorithm containing difference recurrence relations

- (K)

x x, + h, x, 2

, -d + i) y, + q, y, 2,

where x „

 Y, + H, Y, 2 x, Y0 I.

ABOUT)

SP

Ј

sl to

OP

x y - value after the first

steps

1st iteration

., - {

I С

at x (y,,

Oh when y -1 x

3154521

 , 2, ..., n - serial number

iteration;

n is the number of bits of the argument;

q, q. - forward and reverse code of the value comparison signal

The result is

and y

 x yn -

Vx

It is known that when calculating with the help of algorithm (1), there is an elongation of values by an amount K., determined by the relation

TO; - P (1 + 2-U

Uo

Thus, the obtained values of x, y are 1 times K. times the true value of the length of the vector after rotation, therefore, the correction of the obtained results, i.e. is required

i l i find x. “-, y i b. i

-. When properly K. i

an organized division operation must be equal to 1

where the number Z is the quotient of the division can be represented as a product, i.e. Z P (1- C-,).

, 1-0

I 1 with x1.

Then the algorithm (2) to correct the results obtained when implementing the algorithm (I)

R

- I

x, G; X- 2;

V, - Oh, 1-2

(2)

y - value after the first step of the i-th inte

0

five

0

five

0

five

0

45

50

five

84

radios as a result of the correction.

Device p Get up as follows.

Consider the operation of block 1, the iteration calculation. In the first cycle, the value of x0 x is entered into the register 12 at input 10, the value of y0 1 is recorded at input 11 with the arrival of a pulse at synchro 1, the values X)} x, 1 are recorded in registers 12 and 13. Registers 16 and The 17 shifts are connected to the corresponding second inputs of the adders 14 and 15 in such a way that the values Xc and aus are shifted to the inputs with a shift one bit to the right, besides, the first input of the adders 14 and 15 receive the values x0 and y0.

The x and y 1 values obtained at the outputs of the adders 14 and 15 go to correction block 2, where the result is corrected. The operation of adders 14 and 15 is controlled by the values of q- and c (which, by comparing the values of x. Y., Are determined in block 18, with the arrival of a pulse on synchronous input 2, in block 18 of the difference analysis, the values and y are recorded, and s when the pulse arrives at the sync input, the 3 values of the numbers o and o are transmitted to control the adders 14 and 15. In the second cycle, the calculation results are recorded from the first correction unit 2 to the second unit 1, i.e., the obtained values Y j + f and y after the first the steps of the i-th iteration as a result of the correction from the first block 2 are written to the register S 12 and 13 of the second block 1, respectively. At the same time, the secondary loop codes are entered into registers 12 and 13 of the first block 1. In the first block 1, the first iteration is executed on the second operand, like in the first cycle, the first iteration is performed on the first operand, and The second iteration is performed on the first operand in the second block 1. In the third cycle, the calculation results from the first and second correction blocks 2 are written to the second and third blocks 1, respectively, and simultaneously calculated in registers 12 and 13 of the first block 1 iteration enter codes of the third operand. In the first block 1, the first iteration over the third is performed.

their operand, PO second - and throats and iteration over the second operand, in the third - the third iteration over the first operand. In the future, the results from the previous blocks come in

subsequent blocks, two operands arrive in the first block, and so on.

Consider the work of block 2 correction.

Values of x and y1 at the outputs of the sum

mators arrive respectively in

registers 19 and 20. With the arrival of a pulse at sync gate 4, registers 19 and 20 record the values and y. Registers 23 and 24 shift shift the values of x} and y by one bit to the right, i.e. their multiplication by, and the results (shifted values

x,) are fed to the first inputs of the switches 26 and 27, respectively. The second inputs of the switches 26 and 27 receives signals of logical zero. With the arrival of the pulse at the synchronous input 5, in the difference analysis block 25, the values xf and y1 are recorded, and the arrival of the impulse to the synchronous input 6 is the values of the digits G (0.1 are transmitted to control the switches 26 and 27. The first inputs of the emitters 21 and 22 receive the corresponding values xl, y, and the second inputs of the subtractors 21 and 22 receive the values C- (x 2, respectively. In each correction block 2, the algorithm (2) is computed. In each i-th (i 1,2, ..., n a) iterative block 1 and block 2 of the correction of the shift n one bit to the right is carried out by rigidly connecting the outputs of the bits registers with inputs of shift register bits with a shift by a given number of bits.

Claims (1)

Invention Formula A device for extracting the square root and its reciprocal, consisting of n calculation blocks (where n is the number of argument bits) of the iteration, each of which contains the first and second registers, the first and second adders, the first and second shift registers, the difference analysis unit The resolution enable entries of the first and second registers are connected to the first synchronous input of the device, and the information inputs are connected to the first and second in2, respectively. () g 0 5 0 o five 0 5 8A form in the course of the lm of the third, the nw-years of the first ii of the second registers are connected with the first inputs of the first and second adders, respectively, with the inputs of the first and second shift registers and the first and second information outputs of the difference analysis unit, respectively, the first and The second control inputs of which are connected to the second and third syncro inputs of the device, respectively, and the first and second outputs are connected to the second and third ginhover inputs of the device, respectively, characterized in that, in order to increase the speed Twi, additional correction blocks are introduced in the neg, each of which contains the first and g second registers, the first and second shift registers, the first and second switches, the first and second subtracters, the difference analysis block, with the outputs of the first and second adders i-ro ( i I, ..., In) of the iteration unit are connected to the information inputs of the first and second registers of the i-ro correction block, respectively, whose recording resolution inputs are connected to the fourth synchronized input of the device, the output of the first register of the 1st correction block is connected to the first input of the first subtractor, with the information input of the first shift register and the first information input of the difference analysis block: th correction block, the output of the second register of the 1st correction block is connected to the first input of the second calculator, the information input of the second shift register and the second information input of the difference analysis block 1 -th correction block, the outputs of the first and second shift registers of the 1st correction block are connected to the first inputs of the first and second switches of the same correction block, respectively, the second inputs of which x are connected to the fifth synchronous input of the device, and the outputs are connected to the second inputs of the first and second subtractors of the i-ro correction block, the first and second control inputs of the difference analysis block of the 1st correction block are connected to the sixth and seventh syncrodes respectively devices, and the first and second outputs - with the third inputs of the first and second switches of the same correction unit, the outputs of the first and second The subtractors of the i-th correction block are connected to the information inputs of the first and second registers (i + l) -ro of the iteration calculation block, the outputs J 4 S 6 7 to 9 The first and second subtractors of the n-i correction unit are, respectively, the first and second information outputs of the device.