SU1543546A1 - D-a converter - Google Patents

Abstract

The invention relates to automation and can be used in the construction of precision digital-to-analog converters, as well as instrumentation equipment. The purpose of the invention is to improve accuracy. The D / A converter contains 1 source of reference voltage, the main code-controlled divider 2, two additional code-controlled dividers 3.4, output 11, first 12 and second 13 current-voltage converters, two scaling elements on resistors 20 and 21, input 22 and output 23 tires. A positive effect is achieved due to the inverse connection of the code-controlled divider 3 and the connection of the output of the converter 13 through a scaling element with the inverting input of the converter 12. 1 sludge.

Description

The invention relates to automation and can be used in the construction of precision digital-to-analog converters, as well as instrumentation.

The purpose of the invention is to improve accuracy.

The drawing shows the functional schema of the digital-to-analog converter.

The digital-to-analog converter contains a source of 1 reference voltage, the main n-bit code-controlled divider QL) 2, two additional n-and (n-1) digit bits QD 4i respectively, each QL is made in the form of a resistive matrix ( 5-7) switch groups (8-10), output 11, first 2 and second 13 current-voltage converters, each of which is designed as an operational amplifier (14-16) and feedback resistor (17-19) two scaling elements on resistors 20 and 21, as well as input 22 and output 23 bus

I к / 1 - components of the 1st current, which are mainly coupled KU In the case of ideal transistors 8 and operational amplifiers, cf; at the outputs, the resins of the matrix 5 of the R-2R type should be zero. Due to the residual effects of the switches 8, the zero offset, and the static voltage of the operational condition, the potentials CP | are distinguished by the expression

The resistive matrix 6 is made i (ja resistors 24 and resistor 25, the resistive matrix 7 is made on resistors 26, 30 n. A-t r- + a (I-r- + IL + U

, rc-tnf D1 1111 (SDLST

resistor 27 and resistors 28.

Digital to analog converter

where

-inverse zero digits

works as follows.

The switches 8 connect the outputs of the resistive matrix 5 of the R-2R type either to the common bus or to the summing point of the output converter 11 current - voltage depending on the control code Јa ,, ..., a ;, .., ap) n | ine 22, where a; e {0; one.

The output voltage of the converter is formed at the output of the operational amplifier 14 (bus 2.3) in accordance with the expressions

Roc (I RM,)

out + iyyh i

mg n

, + ismo

(one)

; 1; Ы;

1 "1

e R

wasp

you

and

& ЫХ4

the resistance of the feedback resistor 17 of the op-amp 14; output current of the main KUD

2;

the output voltage of the first current-voltage converter 12;

Ml

cm

I: R ,,,, is the resistance of the first scaling element on the resistor 20; the bias voltage of the zero of the operational amplifier 14 is the current of the 1st discharge of the main KUD 2;

1b, q); - potential of the i-ro KUD 2 node and potential at the output of the i-ro discharge of resistive matrix 5 of the R-2R type;

2R - discharge resistance

the resistor main KUD 2;

Im.

Ic / 1 is the components of the 1st discharge current of the main ACC 2, which are branched into the additional ACC 3 and 4. In the case of ideal switches 8 and the operational amplifier 14, the potentials are cp; at the outputs of the resistive matrix 5 of type R-2R should be zero. Due to the residual resistances of the switches 8, the bias zero voltage and the voltage of the statism of the operational amplifier 14, the potentials CP | differ from zero and are determined by the expression

n. a-t r- + a (I-r- + IL + U

), (2)

s 35 s-

where

40

TO

“;

about

-inverse value of the digit digit of the code;

- residual resistances of switches 8 of the 1st digit, respectively, at and

- voltage error of the statism of the operational amplifier 12;

- gain factor ..

amplifier 14 without feedback.

Under the action of these potentials 45, the nodal potentials of ECM 2 are changed by the value U.U; . Therefore, the output current of the main KUD 2 and its error & I .., "can be represented as

wOf K4

w And

Öp g. , t.j. A g

f u LBbix

i - and UI h "-355 21a, AU; -Z: a, tp,) 50

out

(3)

 i n-

55

OUT

h

-21a; iK; - 21 a, iKa,

.

42- .... L .1

 2RX

(

(2R

),

2R /

..aluU; - - r-a ,, - (k + l;)

(four)

where R ,, R. 51543546

resistance resistors

24 junior and resistor

25 senior bits

KUD 3; -

R is the resistance of the discharge resistor 28 of the additional ECD 4; EO - source voltage 1

the reference voltage for To compensate for the first term of expression (4), the additional KUD 4 performs weight summation of the potentials vs; (1 1, p-1), similar to the same weight sum of the potentials, mainly KUD 2, while the potential 1- KUD 4 node is equal to &U; / 2. Therefore, when connecting the outputs of a resistive matrix (the resistance value of resistors 26-28 which satisfy the condition 2Ra7 4R4g) using switches 10 either to the common bus or to the summing point of the first converter 12, the current-voltage, to the summing point of the second operational amplifier 15 output

KUD 4 current flows

t and-f

W sch; yi;

To compensate for the second term of the expression (4), the switches 9 connect the outputs of the resistive matrix 6 either to a common bus or to a summing circuit.

point of the second converter 13 is voltage. Under the action of the output voltage of the third operational amplifier 16, a current flows to the summing point of the second operational amplifier 15

Ay where

Uftbix 1 RM R,

ROC2., 1

RMCL R,

n-i

OCQ.

-but-.,

nineteen

R

ma

resistance of the feedback resistor of the third operational amplifier 16; the resistance of the second scaling element on the resistor 21.

As a result, the output voltage of the first current-voltage converter 12 is

tm-t

IVI | G ROCI

Rr

n-i

 -fS-2; u;

n-l

M, f.

+ Roc, 5-5

where is ROC | The resistance of the feedback resistor 18 of the second opamp 15.

Taking into account (1) - (5) rightly

When providing R 2R BocLlR.Mi / RfiCLRoc.l

-, DJ.D VDD

ROCt + RMi

RA4 RMu

R0 2R (-

R "(R MI

 R (RM

one)

output voltage of digital-to-analog converter

And -F But

U8b№ hOR

2m +

Thus, compared with the known, the proposed converter with the same speed has a higher linearity of the conversion function, since (when compensating for errors from residual resistances of keys, bias voltage zero and error voltage the output amplifier statics), the code-dependent error is the output voltage of the DAC does not occur.

Claims (1)

Invention Formula A digital-to-analog converter containing a source of reference voltage, a main n-bit code-divider, a first (n-1) -discharge and a second n-bit additional code-controlled dividers, first, second, and output current-voltage converters the latter of which is made up of a first operational amplifier and a first feedback resistor connected between the output and the inverting input of the first operational amplifier, the output and non-inverting input of which are the output bus and w hydrochloric zero potential, the first transducer current-voltage formed as the second operational amplifier and a second resistor ob- connection between the output and the inverting input of the second operational amplifier, the output of which is connected to the inverting code of the first operational amplifier through the first scaling element, made in the form of the first resistor | , the second current-to-voltage converter is made as a third operational amplifier and a third feedback resistor connected between the output and the inverting input of the third operational amplifier; the output and non-inverting input of which are connected respectively to the first output of the second scaling element made in the form of a second resistor, and with a zero-potential bus, the main n-bit code-control divider is made in the form of a first group of switches and a resistive R-2R matrix of n-1 after-d ( effectively connected resistors, p-bit resistors and a resistor, the first pins of the nJM-bit resistors, besides the n-th, are connected to the first pins of the corresponding (the connecting resistors, the first of the n-th discharge resistors with the second output (ir -) - ro resistor and is connected to the first output of the voltage source, the second output of which is connected to the zero potential bus, the second pins of the resistor R-2R resistors are connected to the information the inputs of the corresponding switches The first group of switches, the first outputs of which are connected to the zero potential bus, and the second outputs are connected to the inverting input of the first operational amplifier, the R-2R resistor matrix correction resistor is connected between the zero potential bus AND the first output of the first resistor of the resistive matrix of the type R-2R, the first p-1 bit additional code-controlled divider is made on the second group of switches and the first resistive matrix made as a group of n-1 series-connected resis tori of the same resistance, p-1 groups of two successively connected resistors of the same resistance and an additional resistor, the first output of which is combined with the first output the first resistor of a group of n-1 series-connected resistors of the same resistance, and the second output is combined with the first outputs of the switches of the second group of switches and is connected to the zero potential bus, the combined first terminals of the resistors i-th, except for (p-1) -th groups of p-1 groups of two series-connected resistors are connected to the second output of the 1st, except for (nl) -ro resistor, a group of p-1 series-connected resistors of the same resistance, the combined first terminals of the resistors (p-1) and groups of the -1 groups of two series-connected resistors are connected to the first output (p-1) of the group 1 p-resistor of the series-connected resistors of the same resistance, the second output of which is connected to the zero potential bus, the second terminals of the first and second resistors of the i-th group From n-1 groups of two series-connected resistors are connected to the information inputs of 1 switches, respectively, the first and second groups of switches, the second outputs of the switches of the second group of switches are connected to the investment the rotating input of the second operational amplifier, the non-inverting input of which is connected to the zero potential bus, the second n-bit additional code-controlled divider is made on the third group of switches and the second resistive matrix, made in the form of n resistors, the first terminals of which are connected to the third switch groups, the first outputs of which are connected to a zero potential bus, and the corresponding control inputs are combined with the control inputs of the corresponding switches of the first and second switch groups and are input bus, characterized in that, in order to improve accuracy, the second terminals n of the resistors of the second resistive matrix are connected to the information inputs of the corresponding the switches of the first group of switches, the second output of the second resistor is connected to the inverting input of the second operational amplifier, Vto91543546io ry switch outputs third to i 1,2,. „., (n-1); Rn - resistance switch groups are connected to the nth resistor of the second resistive inverting switch by the input of the third operational matrix, RJ is the i-ro resistance the amplifier, and Rn RJ, with the resistor of the second resistive matrix.