SU1532964A1 - Training device - Google Patents

Abstract

The invention relates to training devices and allows expanding the didactic capabilities of the training device by automatically controlling the correctness of the operation of the combinational circuit under study (CS). A positive effect is achieved due to the introduction of an (N + M) -bit memory block 7 for storing the truth table and used for generating N-bit binary sets of input variables of the CC under study and the corresponding M-bit values of the Boolean functions the comparator 8, which provides for each N-bit binary set of input variables of the studied QC, a comparison of the M-bit output code combinations of this circuit and the corresponding M-bit values of the Boolean functions, element 9, controlling the process of checking the correctness of the work of the investigated CS depending on the result of the comparison, and the third indicator 10. The proposed device contains a console 1 student, a set of logic elements in block 4 of the simulation of the studied circuits, three indicators 2, 3, 10, a generator of 5 clock pulses, counter 6, memory block 7, digital comparator 8 and logic element AND 9. 1 Il.

Description

element 9, which manages the process of checking the correctness of the work of the investigated CC depending on the result of the comparison, and the third one,. Dicator 10. The proposed device contains the remote 1 student, set

logic elements in block 4 of simulation of the studied circuits, three indicators 2, 3, 10, generator of 5 clock pulses, counter 6, block 7 of memory, digital comparator 8 and logical, element 9. 9. Il, 1 tab.

The invention relates to educational and laboratory equipment designed to study the synthesis and analysis of combinational circuits used in the construction of computer aids.

I The purpose of the invention is to expand the didactic capabilities of the training device by automatically ontrol the correctness of the research work of the CS.

The drawing shows the structure of the device for training.

The training device contains a student console 1, made up of the first 2 and second 3 indicators, and a set of logic elements in block 4 of the simulation of the studied circuits, generator 5 (clock pulses), counter 6, memory block 7, comparator 8, element And 9 and the third indicator 10.

The device works as follows.

The student synthesizes the combinational circuit (CS), for example, according to a given truth table, collects the CS using a set of logic elements of the console 1, and connects the inputs of the studied CS to the inputs of the console 1, the outputs to the outputs of the console 1. At the stage of preparing the device in the unit 7, the specified truth table is loaded, and the first bits are loaded with the binary sets of input variables of the synthesized QS, and the lower bits - the values of the Boolean functions implemented by the synthesized QS corresponding to these sets.

The table gives the coding of a memory device for studying the combination conversion of a four-bit Gre code into a binary-decimal code.

When the device is turned on, the counter 6 forms a binary code combination, which arrives at the address inputs of block 7 and reads the contents

five

0

0

Q 5

five

0

five

addressed by this code combination of the row of the storage matrix of block 7. Under the influence of the code combination formed in this way on the higher output bits of block 7, the combining circuit under study forms a code combination arriving at one input of the comparator 10, the other combination of which receives the code combination removed from the lower output bits of block 7, and, consequently, the corresponding binary input variables at the input of the combinational circuit. In the case of coincidence of the signals at the inputs of the comparator 8, indicating the correct operation of the synthesized combinational circuit on the formed set of input variables, the comparator 8 generates a signal that ensures the passage of the next signal from the output of the generator 5 through the element 9 to the input of the counter 6. As a result, the contents of the counter 6 is incremented by one and from block 7 the contents of the next row of the storage matrix are read, corresponding to the next set of input variables of the Raman under study circuits, etc.

The considered process of checking the correctness of the QS under study occurs if the learner has learned the QS synthesis well, so that the QS synthesized and assembled by him corresponds to a given truth table, and therefore the comparator 8 for each set of Q input variables matches the combination of code combinations on his inputs.

Insufficiently profound mastering of the synthesis of the CS leads to the fact that the synthesized by the trained CS does not correspond to the truth table, as a result of which at least one of all possible sets of input variables of the studied CS there is a mismatch of code combinations at the inputs of the comparator 8. At the same time, the latter produces a signal , prohibiting in element 9 the passage to the input of the counter 6 pulses of the generator 5. Thus, it is forbidden to switch to a new set of input variables of the investigated, KS. At the same time, indicator 2 presents the input code combination of the CS, indicator 3 shows the output code combination of the COP, and indicator 10 presents the code combination that forms in accordance with the truth table

at the outputs of block 7, which, on the one hand, of the first and second indicators and the ron block, informs about the incorrect simulation of the studied circuits, the genetics of the CS, and on the other hand, the facilitator and the counter that distinguishes the error so for the purpose of expanding

the didactic capabilities of the device, the analysis of the CS in the proposed 20 WA, a memory block is inserted into it, the device is implemented in the same way as in the training of synthesis, except that the learner assembles the specified CS using a set of logical elements of the console 1, and in block 7 loads the truth table found in the stage of solving the problem posed. of this combinational circuit.

Thus, automatization - control of the correctness of the work of the studied CS in the proposed device eliminates the participation of the trainee in the execution of such

the parator, the And element and the third indicator whose input is connected to one output of the memory unit connected to the first input of the comparator, the second input 25 of which is connected to the output of the modeling unit of the studied circuits and the input of the second indicator, and the output to the first input of the And element, the second the input of which is connected to the output of the generator, and the output to the input of the account 30

The address input of the memory unit is connected to the output of the counter, and the other output is connected to the inputs of the first indicator and the next

the correct operation of the investigated COP

required in accordance with the truth table of sets of input variables and comparison for each such set of code combinations at the output of the CS with the corresponding code combinations of the truth table, which ultimately provides for the expansion of didactic capabilities of the device.

Inventory Formula

A training device containing a student console consisting of

va, a memory block,

the parator, the And element and the third indicator, the input of which is connected to one output of the memory unit connected to the first input of the comparator, the second input of which is connected to the output of the modeling unit of the studied circuits and the input of the second indicator, and the output to the first input of the And element, the second the input of which is connected to the output of the generator, and the output to the input of the account

The address input of the memory unit is connected to the output of the counter, and the other output is connected to the inputs of the first indicator and the next

Claims (1)

Claim A learning device comprising a learner’s console, consisting of eds of the first and second indicators and a modeling unit for the circuits under study, a generator and a counter, characterized in that, in order to expand the didactic capabilities of the device, a memory unit, a comparator, an And element, and a third are inserted into it an indicator, the input of which is connected to one output of the memory block connected to the first input of the comparator, the second input 25 of which is connected to the output of the simulation block of the circuits under study and the input of the second indicator, and the output is the first input of the electronic ment and the second input of which is connected to the generator output, and an output - to the input of the counter, the address input of the memory block connected to the output of the counter and the other output - with pervogo'indikatora and subsequent circuits simulation unit inputs. 35 g Line number Address Data The cop • Inputs Outputs 3 1 and 0 4 to. L .LI. 0 0 0 0 0 0 0 0 0 0 0 0 0 0? 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 2 0 0 1 0 0 Ό 1 1 0 0 0 1 0 3 0 0 1 1 0 0 1 0 0 0 0  1 1 4 0 1 0 0 0 1 1 0 0 0 1 0 0 5 0 1 0 1 0 1 1 1 0 0 1 0 ' 1 6 1 1 0 0 1 0 1 0 0 1 1 0 7 0 1 1 1 0 1 0 0 0 0 1 1 1 8 1 0 0 0 1 1 0 0 0 1 0 0 0 9 1 0 0 1 1 1 0 1 0 1 0 0 1 10 1 0 1 0 1 1 1 1 1 0 0 0 ‘ 0 eleven 1 0 1 1  1 1 1 0 1 0 0 0 1 12 1 1 0 ' 0 1 0 1 0 1 0 0 1 0 thirteen 1 1 0 1 1 0 1 1 1 .0 0 1 1 14 1 1 1 0 1 0 0 1 1 0 1 0 0 fifteen 1 1 1 1 1 0 0 0 1 0 1 0 1