SU1531072A1 - Device for program control of four-phase stepping motor - Google Patents

Abstract

The invention relates to automation and computing and can be used to control machines equipped with stepper motors. The purpose of the invention is to increase the uniformity of movement, the accuracy of processing fractional steps and the uniform distribution of the moment across the field of a four-phase stepper motor with an unsaturated magnetic system. The device contains multiplexers 1.2-1.4 of the first group, phase windings of the engine 2.1 - 2.4, counter 4, multiplexers of the second group 5.1 - 5.3, decoder 6, elements 7.1 7.1 - 7. (4N-2), bus of a single logical potential 8, bus 9 zero logical potential. 7 il.

Description

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The invention relates to automation and computing and can be used to control machines equipped with stepper motors.

The purpose of the invention is to improve the uniformity of motion, the accuracy of working out fractional steps and the uniform distribution of the moment across the field of a four-phase stepper motor with a non-priced magnetic system.

4 ″ g.1 shows the functional diagram of the device for the general case when the fragmentation factor is equal to Cor 3n, where n “1,2,3, ... ,, - in FIG. 2-A is the same, for the cases respectively KJP 3 (), K j, b (), K „p 9 (); in fig. 5-7 - temporary diagrams SzI formed phase currents and paths w of resulting moments for the cases, respectively, K, p- 3 (), 6 (), Kdr-9 (n

The device (Figures 1-4) contains multiplexers 1.1-1.4 of the first group of outputs of which are connected (directly or through appropriate power amplifiers) to the corresponding phase windings 2.1-2.4 of the motor, counter 3, the clock input of which is connected to the input of high-frequency clock pulses fg, the reversive counter 4, the outputs of the two most significant bits of which are connected respectively to the control inputs of all multiplexers 1.1-1.4, and the inputs of the clock and reverse, respectively, to the inputs of the low-frequency clock pulses and the roar Sa Rev., multiplexers 5.1-5.3 of the second group, the control inputs of which are connected respectively to the outputs of the lower bits of the reversible counter 4, the decoder 6, the inputs of which are connected to the outputs of the non-reversible binary counter 3, and logic gates And 7.1-7. ( 4p-2), the first input of the first of which is connected to the first output of the decoder 6, the first input of each subsequent element And 7 is connected to the output of the previous element And 7, the second inputs from the first 7.1 to 7. (4n-2) -th, 7. ( 4p-2) elements And are connected to the outputs of the decoder 6 from the second (4n-1) -th respectively -retarded, the first, second, ..., (Sn-1) -th, Sn-th multiplexer data inputs connected respectively to 5.1 vrsodami elements and

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five

five

7. (p-1), 7.n.,.,., 7. (4n-3), 7, (4n-2), and the output - with the fourth, first, second, third information inputs, respectively, multiplexers 1.1-1.4 , first, second, ..., (p-2) -th, (p-1) -th information inputs of multiplexer 5.2 are connected respectively to the outputs of the elements And 7. (p-1), 7. (p-2), ..., 7.2, 7.1, p-th information input - with the first output of the decoder, (n + 1) -th, (n + 2) -th, ..., {2n + 1) -th information inputs with bus 8 of a single logical potential 8, (2n + 2) -th information input - with the first output of the decoder, (2n-3) -th, (2n + 4) -th, ..., 3nth information1C1on inputs - respectively with exits ale And 7.1,7.2, ..., 7. (), and the output - with the third, fourth, first, second information inputs of the multi-plexor 1.1–1.4. The first input of multiplexer 5.3 is connected to the first, second, third, fourth information inputs of the multiplexer 1.1-1.4, respectively, and connected to the bus 9 of zero logical potential, the second, third, ..., 3nth information inputs of the multiplexer 5.3 are connected respectively to the outputs of the elements 7. And (4n-2), 7. (4n-3), ..., 7.n, and the output with the second, third, fourth, first information inputs, respectively, multiplexers 1.1-1.4.

The device works as follows.

The high-frequency clock sequence fg is continuously fed to the input of the irreversible binary counter 3. As a result, the outputs of the decoder 6 are formed periodic code combinations with one zero and 4 n-2 units, and the outputs of the elements And 7.1-7. (4n-2) - rectangular high-frequency latitude-modulated signals (1GM-signals) with a duty cycle, respectively

4p-2 4p-3 2 g,,

, 7. These shsh-sig0 4p

4p

4p 4p

fillers and signals from the first

porosity encoder

go to the corresponding information inputs of multiplexers 5.1-5.3. The initial condition is a c. State in which reversible counter 4 is in the zero state. For all

The control inputs of the multiplexers 1.1-1.4 and 5.1-5.3 from all the outputs of the lower and lower bits of the reversible counter 4 receive zero potentials and, consequently, their first channels are selected. Present at the first information inputs of multiplexers 5.1 and 5.2 NMT-signal

duty cycle

4p

and the zero potential at the first information input of multiplexer 5.3 through their outputs and the first inputs of certain multiplexers 1.1-1.4 goes to the phase windings 2.1-2.4. As a result, through the second 2.2 and third

2.3 motor phases flow currents

2

T- / N, and in the other two phases 2.1

and 2.4 no current. This state corresponds to point O in FIG. 56

65.76.

With the arrival of the first Sn-1 low-frequency pulses at the input of the counter 4, the numbers 1,2, ..., Sn-1 are alternately recorded in it. As a result of this, the information inputs of multiplexers 5.1-5.3 are alternately selected from the second to the third one. In this case, in multiplexers 1.1-1.4, the first information inputs remain selected. By virtue of this, phases 2.1-2.4 of the engine alternately receive certain SH1-signals, leading to the flow of the corresponding currents through them. These states correspond to the point 1-Зп-1 in FIG. 56,

66.76.

This completes the first quarter of the four-phase motor control cycle, as a result of which Sn-1 fractional steps of T are worked out, where ci is the main

(constructive) engine pitch, a, 2,3, ...

The subsequent (Sn) low-frequency pulse sets in zero states the lower bits of counter 4, the conversion factor of which is equal to Sn, and generates a transfer pulse for recording in the higher bits of this counter, the conversion factor of which is 4, digits 1. Due to this, second information inputs of multiplexers 1.1-1.4. In the rhythm of the arrival of Sn-1 low-frequency pulses f on

ten

5310726

the input of the counter 4 at the n + l outputs of its lower-order bits are formed, codes that allow alternately selecting the information inputs of multiplexers 5.1-5.3. As a result, certain MIM signals alternately arrive at phases 2.1–2.4 of the motor, leading to the flow of corresponding currents through them. These conditions correspond to the point Zp-6p-1 in FIG. 56, 66, 76. This completes the second quarter of the engine control cycle, as a result of which the subsequent 3p-1 fractional steps are worked out.

The next third and fourth quarters of the device’s cycle of operation are similar to the first two quarters of the cycle described. The difference lies only in the fact that by the older bits of counter 4, the third and fourth information inputs of multiplexers 1.1-1.4 are selected.

Upon completion of the complete control cycle, the counter 4 is reset to zero and the entire system is reset to zero.

To ensure the reverse direction of rotation of the motor (reversing) is changed to the reverse logic potential at the input of the reverse of counter 4,

20

25

thirty

The frequency of the pulses applied to the fg input of the high-frequency clock is selected based on the magnitude of the electromagnetic time of a given engine, and the frequency of the pulses applied to the bus of the low-frequency control pulses is selected in accordance with the required speed of rotation of the rotor of the engine.

Formula and 30 b re shadow

A device for software control of a four-phase stepper motor, containing the first, second, third and fourth multiplexers of the first group, the outputs of which are connected to the corresponding phase windings of the motor, a non-reversible counter, the clock input of which is connected to the input of the high-frequency clock pulses of the device, and a reversible counter, the outputs of the two high bits of which are connected respectively to the control inputs

The first, second, third, and fourth multiplexers of the first group, and the clocking and reverse inputs are connected respectively to the low-frequency clocking and reversing device inputs, different from the fact that, the goal is to increase the uniformity of motion, the accuracy from fractional steps, and the uniformity of distribution moment over the field of a four-phase stepper motor with an unsaturated magnetic system, additionally contains three multiplexers of the second group, the control inputs of which are connected respectively to the output m low bits of the reversible counter, deingfrator, the inputs of which are connected to the outputs of the counter, 4n-2 elements And, where, 2,3, ..., the first input of the first of which is connected to the First output of the decoder, the first input of each subsequent element And connected with the output of the previous element And, the second inputs from the first through (4n-2) -th elements And connected to the outputs of the decoder from the second to (4n-1) -th, respectively, the first, second, ..., (Zn-1) - th, Sn-th information inputs of the first multiplexer of the second group are connected respectively to the outputs (nl) -ro, n-th, ..., (4P-3), ( 4p-2) -th elements And, and the output - with the fourth, first, second, third information inputs of the first, second, third, fourth multiplexers of the first, respectively

five

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group, first, BTOpoi i,. . . , (p-2) -th, (n-1) -ii information passes of the second multiplexer of the second group are connected respectively to the outputs of (p-1) -th, (p-2) -g o,. . ., the second, the first elements 11, the nth information input - with the first output of the decoder, (n + 1) -th, (PCh-2) -th,. ,., (2n + 1) -th information inputs - with a bus of a single logical potential, (2n + 2) -th informational input - from the first 1) 1st output of the decoder, (2n + 3) -th, (2n + 4) - th, ..., Sn-th informational inputs - respectively with the outputs of the first, second, ... (n-2) -th elements of I, and the output - with the third, fourth, first, second informational inputs of soch vest- first, second, third, and fourth multiplexers of the peri-group, the first input of the third multiplex cluster of the sluggish group is connected to nepjjhiM, the second, third, fourth 1P1phoma1, ionic inputs, respectively first, second, third, fourth multiplexers of the first group and connected to the bus of zero logical potential, the second, third,. . . Sn-ii information inputs of the third multiplexer of the second group are connected respectively to the outputs (An-2) -th, (4p-3) -th, ..., n-th elements I, and the output - with the second, third, quarter, first information inputs, respectively, of the first, second, three, fourth multiplexers of the first group.

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Claims (1)

The claims 45 A device for programmed control of a four-phase stepper motor, comprising the first, second, third, and fourth multiplexers 5θ of the first group, the outputs of which are connected to the corresponding phase windings of the motor, a non-reversible counter, the clock input of which is connected to the input of high-frequency * 5 pulses of the device’s clock pulses, and a reversible counter the outputs of the two high-order bits of which are connected respectively to the control inputs Ί 1 53) 07 2 of the first, second, third and fourth multiplexers of the first group, and the clock and reverse inputs are connected respectively to the inputs of the low-frequency clock pulses and the reverse of the device, which differs gem, which, έ aims to increase the uniformity of movement, the accuracy of working out fractional steps and uniform distribution of torque over the field of a four-phase stepper mover with an unsaturated magnetic system, additionally contains three multiplexers of the second group, control inputs of co-; of which are connected respectively to the outputs of the least significant bits of the reversible counter, a decoder whose inputs are connected to the outputs of the counter, 4n-2 elements And, where η = 1,2,3, ..., j, the first input of the first of which is connected to the first output of the decoder, the first input of each subsequent element And is connected to the output of the previous element And, the second inputs from the first 2 to (4n-2) th elements And are connected to the outputs of the decoder from the second to (4n-1) ~ th, respectively, the first, second, .. ., (Зп-1)-й, Зп-й information inputs of the first multiplexer of the second group are connected respectively respectively, with the outputs of the (n-1) th, n-th, ..., (4n-3), (4n-2) -th elements of And, and the output with the fourth, first, second, third information inputs, respectively . Accordingly, of the first, second, third, fourth multiplexers of the first group, the first, second, ..., (p-2) -th, (p-1st information inputs of the second multiplexer of the second group are connected respectively to the outputs of (p-1) -th , (n-2) -th, ..., second, first elements And, n-th information input - with the first output of the decoder, (n + 1) -th, (n + 2) -th, ..., (2n + 1) -th information inputs - with a bus of a single logical potential, (2n + 2) -th information input - with the first output of the decoder, (2n + 3) -th, (2n + 4) ~ th, .. ., Zn ~ th information inputs - respectively, with the outputs of the first, second, ... (p- 2) of the And elements, and the output with the third, fourth, first, second information inputs of the first, second, third, 0 fourth multiplexers of the first group, respectively, the first input of the third multiplexer of the second group is connected to the first, second, third, fourth information inputs, respectively the first, second, third, fourth multiplexers of the first group and is connected to the bus of zero logic potential, the second, third, ... Zn-th information inputs of the third multiplexer of the second group are connected respectively to you the odes of the (4p-2) -th, (4p-3) -th, ..., p-th elements 11, and the output with the second, third, fourth, first information inputs, respectively, of the first, second, third, fourth multiplexers of the first groups. fig 2 Cha Fie.Z Fig 5 ~ α