SU1522423A1 - Scanning device - Google Patents

Abstract

The invention relates to film and television technology. The purpose of the invention is to increase the linearity and stability of the sweep. The sweep device contains a clock rr 1, counters-dividers 2, 3 and 4, line and frame decoders 5 and 10, phase detector 6, block selection 7 of the frame sync pulse interval, block of coincidence 8, trigger 9, adders 11, 14, 18 , 21, 23, and 26, integrators 12, 15, 19, and 22, pulse amplitude modulator 13, power amplifiers 16 and 24, horizontal and frame deflection coils 17 and 25, balanced modulator 20, variable resistors 27 and 28, and cathode ray tube 29. The goal is achieved by providing independent adjustment of the linearity of the deflection and of the pillow and sayings on given raster areas. 3 il.

Description

The invention relates to film and television equipment, in particular to high-quality electron beam scanners of a cathode ray tube for various film and television devices, and can be used in devices for recording a television image onto film.

 The aim of the invention is to improve the linearity and stability of the sweep by providing independent adjustment of the linearity of the deviation and pincushion distortion in the given raster areas.

FIG. Figure 1 shows the structural electrical circuit of the sweep device; in fig. 2 and 3 - structural-electrical circuits of adders.

The sweep device contains also a generator 1, first 2, second 3 and third 4 dividers, a string decoder 5, a phase detector 6, block 7 for selecting the slot of the clock sync pulse, block 8 matches, trigger 9 frame decoder 10, sixth adder 11, fourth integrator 12, amplitude-pulse modulator 13, second adder 14,: first integrator 15, first power amplifier 16, horizontal, horizontal deflection of a coil 17, third adder 18, second integrator 19, balance modulator 20, fifth adder 21, third integrator 22, fourth total p 23, the second power amplifier 24, Yushchuk frame deflection coil 25, a first adder 26, first and second variable resistors 27 and 28 and a cathode ray tube 29.

Adders 11 and 18 (Fig. 2) contain an operational amplifier 30, a group of variable resistors 31 and a group of permanent dividers 32.

Adders 14 and 21 (FIG. 3) contain an operational amplifier 33 and a group of variable resistors 34. The sweep device operates as follows.

From an external source of clock signals to the inputs of the phase detector 6 and the block 8 of coincidence, the line and frame sync signals are respectively supplied. A clock generator 1 generates voltage pulses with a frequency of 8 pages, where f is the horizontal scanning frequency.

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The counter-divider 2 is a frequency divider by 8. The output of one of the bits of the counter-divider 2, which contains pulses with the following frequency 2f, is connected to the input of the counter-divider 3, which is a frequency divider by 82. Counter-divider 4 has an adjustable division factor depending on the signal at its control input connected to the trigger output 9. Depending on the magnitude of the specified signal (O or 1), the total division ratio of counters divisors 3 and 4 can be 625 or 626 ( for broadcast standard ) For forming a raster with other parameters decomposition coefficients and the frequency dividing counters oscillator generation will be different).

Adders 11 and 18, 14 and 21 are adjustable. Adders 11 and 18 are identical to each other and have two groups of inputs - a group formed by variable input resistors 31 that serve to adjust the curvature of the parabola in different parts of the raster. and for accurate correction of various raster distortions. These inputs are connected to the outputs of the corresponding decoder 5 or 10. One of the inputs of each of the adders 11 and 18 is connected to a variable resistor 28 or 27, respectively, used to adjust the symmetry of the parabolic signal produced for correcting distortions at a particular sweep coordinate. The three input resistors 31 in each of the adders 11 and 18 are constant, and their resistance values refer to each other as 4: 2: 1. These resistors are connected to the bits of the counters of dividers 4 and 2, respectively.

These resistors image-comfort as part of each of the adders 11 and 18 digital-analog converter. As a result, when the device operates, as the magnitude of the code accumulates on the counters divider 2 and 4, a stepwise linear increase in voltage occurs at the output of the adders 11 and 18.

The adders 14 and 21 are constructed in a similar pattern (Fig. 3), but all of their input resistors 34 are variable and are used for non-dependent linearity control in different raster sections.

Thus, adders 11 and 18, by introducing variable input resistors 31 and three constant input resistors 31 with a ratio of 4: 2: 1, connected to the outputs of the respective counters-dividers 2 and 4 and decoders 5 and 10, into them Based on the summation of the input signals, three main functions:

converting the incoming from the counter-dividers of the code into a linear (stepwise) increasing voltage at the input of the adder;

adjustment by adjusting the corresponding variable input resistors of the shape of the parabolic signals obtained as a result of integrating the signals from the output of the adders, on one or another part of the raster in order to accurately compensate for pincushion and other distortions;

adjusting the symmetry of the parabola relative to one or the other side of the raster by means of variable resistors 27 and 28 connected to adders 18 and 11, respectively.

The clock generator 1 generates pulses with the following frequency B f which are fed to the input of the counter-divider 2, which divides the frequency into 8. The output of one of the bits of the counter-divider 2, which contains pulses with the following frequency 2 fpT.p, is connected to counter divider 3, which is a frequency divider by 82. divider 4 has an adjustable division factor, depending on the magnitude of the signal at the control input of divider 4, i.e. from the state connected to its control to what the input of the trigger 9. The counters-dividers 3 to 4 form a frequency divider with an adjustable division factor of 625/626.

To the input of the phase detector 6, the so-called zero output of the line decoder 5 is podkhyuchen, on which there is a signal corresponding to. Frame damping pulses. Through the phase detector 6, the frequency and phase of the clock generator 1 are adjusted to the standard line frequency determined by

 Led by external horizontal sync signal.

The device also contains a digital feedback circuit formed by dividers 3 and 4, block 7 in the division of the frame sync pulse, block 8 matches and trigger 9, performing exact

0 adjustment of frequency and phase (synchronization) of framed frame dust with personnel sync signal. The gradual shift (raid) of the phase of the pulses by the duration of the half-line over the period by

5, the output of the divider counter 4 (mpeghed bit), connected to the input of the block 7 for the frame sync pulse, leads to the coincidence of the frame syncro and the frame sync pulse and for the trigger of the coincidence circuit 8, triggering the trigger 9 and switching to the trigger 9 and triggering the trigger of the coincidence circuit 8 and triggering the trigger 8 and triggering the trigger of the coincidence circuit 8 and triggering the trigger 8 and triggering the trigger 8 and triggering the trigger. the division ratio of counters-dividers 3

5 and 4 from 626 to 625 and thereby adjusting the phase of the frame saw being formed to the external personnel clock signal. The trigger 9 is reset to the zero state by a reset pulse,

0 produced at the output of the counter-divider 4 when it is filled, i.e. at the end of each frame scan period, the trigger 9 is set to the zero state.

The number of outputs available to the line decoder 5 and the personnel decoder 10 is equal to the number of segments or intervals into which the corresponding side of the frame is conventionally divided (for example, seven vertically and horizontally in a real scanner), and in which the shape is independently controlled and amplitudes of corrective parabolic signals by means of variable resistors 27, 28, 31, and 34 included in the adders 11, 14, 18, 21. Accordingly, the duration of the forward stroke (active part)

0 line and frame scan is divided into the same number (seven in the real scanner) time intervals. During each interval, the signal is present only

5 on one definitive output of the decoder 5 and 10, and on the other outputs of the decoder 5 and 10, the signals are zero. In the process of operation of the device, as the counters are divided, the

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Leu 2 and 4 there is a sequential shift of the signal from one decoder output to another (for both frame 10 and line 5). The magnitude of this signal is equal to the logical unit. Thus, during the formation of the forward motion of the saw, the signal from the output of the decoder 5 (10) sequentially runs through the inputs of the adders 18, 14 (11, 21), and the voltage value at the output of one or another adder 18, 14 (11, 21) at each time interval is set by the corresponding input variable resistor from the group of 31 variable resistors of adders 18 and 11 and from the group of 34 variable resistors of adders 14 and 21, on which the signal from the output of the decoder 5 is present during this interval (10 ). The voltage form at the output of the summers 18, 14 (11, 21) will be a stepped function, and the voltage at the input of the adders 18 and 11 will be a stepwise sawtooth shape, respectively, with the personnel and with the horizontal frequency These resistors of adders 18 and 11 are connected to the corresponding counters-dividers 2 and 4 and form analog-to-digital converters as part of adders 11 and 18.

After integrating these signals, respectively, by integrators 12 and 19, piecewise parabolic signals are formed at their output, respectively, with frame and line frequency.

One of the inputs of the adder 14 is fed from the output of an amplitude-pulse modulator 13 lowering quenching signal modulated by a signal of a parabolic form of the frame frequency (lowering damping pulses arrive at one of the inputs of the amplitude-pulse modulator 13 from the zero output of the horizontal decoder 5, and the frame frequency parabola signal is from the integrator output 12). By integrating the integrators 15 and 22 of the signals from the outputs of the adders 14 and 21, the result of the integration is to receive the signals of a horizontal saw, iromodulated by a correcting parabolic voltage

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frequency and frame saw. The line signal thus generated is

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the deviation through the power amplifier 16 enters the horizontal deflecting coil 17. The frame saw signal from the output of the integrator 22 is fed to the input of the analog balanced modulator 20 and simultaneously to the input of the fourth adder 23. To the second input of the balanced modulator 20 a signal of a piecewise line frequency parabola integrator 19 output. At the output of the balanced modulator 20, a correction signal is generated, which is a horizontal frequency parabola modulated by a frame saw. The frame saw signal is summed by the adder 23 with the correction signal and fed through the power amplifier 24 to the frame deflecting coil 25. The adder 26 generates a grid signal used to modulate the brightness of the cathode ray tube 29 and visual control of the linearity of the sweeps.

Claims (1)

Invention Formula A sweep device containing a clock, first counter0 five 0 five 0 five The first, second and second power amplifiers, the outputs of which are connected respectively to the horizontal and vertical deflection coils, the other taps of which are connected to a common bus, characterized in that, in order to improve the linearity and stability of the sweep by providing independent adjustment of the linear deviation and pod-shaped distortions in specified areas of the raster, a phase detector is introduced, the first input of which is the input of the horizontal sync pulses of the sweep device, and the output is connected to the input of the clock generator a, a serially connected coincidence unit, the first input of which is the input of the frame sync pulses of the scanning device, and a trigger, a block for allocating the frame sync pulse, the output of which is connected to another input of the coincidence block, the second and third counters-dividers, line and frame decoders, the first The second and third inputs of which are connected to the corresponding outputs of the first and third counters-dividers, respectively, the fourth and five outputs of which are connected respectively to the input of the rake block and the frame sync pulse interval and with the second trigger input, the output of which is connected to the first input of the third divider counter, to the second input of which the second output of the first divider counter is connected via the second divider counter, as well as the first adder is entered to the first and second - to the rum inputs of which the input of the first counter-divider and the output of the clock generator and the output of the second counter-divider are connected, and the output is the output of the sweep device, successively connected by an amplitude and pulse modulator, the second The mmator and the first integrator, the output of which is connected to the input of the first power amplifier, connected in series to the third adder, correspond to the first, second and third inputs of the first counter-divider, the second integrator, the balanced modulator and the fourth adder, whose output connected to the input of a second power amplifier, a series-connected five adder and a third integrator, the output of which is connected to the combined second inputs of a balanced modulator and a fourth adder, sequentially The sixth adder, connected to the first, second and third inputs, are connected to the corresponding outputs of the third splitter counter, and a quarter integrator, the output of which is connected to the first input of an amplitude-pulse modulator, to the second input of which is connected the second input of the phase detector, the fourth input of the third adder through the first variable resistor and the zero output of the line decoder, the other outputs of which are connected to additional combined inputs of the second and third adders, and the zero output HR decoder coupled to the first input of the fifth adder and through a second resistor peremenny to fourth input of the sixth adder, to whose further inputs connected to additional inputs of the fourth adder and the respective outputs of the decoder personnel. 27/28) ffuS.Z Compiled by I.Gratsianska Editor A.Lezhnik Tehred L.Serdyukova Order 6981/57 Circulation 626 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 1 (21) (rig. 3 Proofreader M.Maksimishinets Subscription