SU1522264A1 - Recursive computing apparatus - Google Patents

Abstract

The invention relates to automation and computing, in particular, to multi-purpose digital-controlled analog computing devices. The purpose of the invention is to improve the performance of the device and expand the scope of its application by performing summation and comparison operations. The recursive computing device contains a register 1 for bit balancing, a comparator 3, a reproducing digital-to-analog converter 4, a synchronization unit 8, keys 1–15, 15–20, 44 and 45, first –– fifth analog switches 21–24, 46, group analog storage elements 31 and 32, first to third sources of reference voltage 33, 47 and 48, integrating capacitor 34, resistive voltage divider 35, operational amplifier 43, adjustable voltage source 46, additional analog storage element 49 and two terminating resistors 50 and 51. Performing new operations — summation and comparison, as well as the simultaneous execution of any computational operation using an operational amplifier, inputting and storing analog signals, improves the performance of the device and expands its field of application. 1 il.

Description

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a third reference voltage source 33, 47 and 48, an integrating capacitor 34, a resistive voltage divider 35, an operational amplifier 43, an adjustable voltage source 46, an additional analog storage element 49 and two terminating resistors 50 and 51. Execution

new operations - summation and comparison, as well as the simultaneous execution of any computational operation using an operational amplifier, input and storage of analog signals can improve the performance of the device and expand the scope of its application. 1 il.

The invention relates to automation and computing, in particular to widely used digital computing devices that can be used for preprocessing analog information, implementing various analog functions, performing addition operations, subtracting analog signals and samples of analog signals, integrating ana signal signals, their conversion into a code and vice versa, as well as for other operations .; and can be used as a multipurpose operating unit in interface systems of analogs and digital computers, in communication systems of digital computers with control objects, information from and to which comes in the form of analog signals.

The purpose of the invention is to increase the productivity of the device and expand its application area by performing addition and comparison operations,

The drawing shows a block diagram of the device.

The device consists of a register of equilibrium 1j supplied with input-output digital information 2, forming digital input-output devices. The register (MPP) 1 also has a comparison input for connecting to the output of comparator 3 (KOM) outputs for connecting to digital inputs of a digital-to-analog multiplex DAC converter 4 equipped with a reference voltage input 5, feedback resistor 6 and output 7. Register control inputs 1 is connected to the first group of outputs of the synchronization unit (CU) 8, the outputs from the first to the sixth 9-14 of which are connected to the control inputs from the first to the sixth keys 15-20 (К15К2 ,, .., К6

.

Q

0

five

respectively). Groups of control inputs of analogue KOMiviyTaTopoB first to fourth 21-24 (AK1, AK2, AKZ, AK4, respectively) are connected to the output groups of block 8 from the second to the fifth 25-28, respectively. The outputs of block 7 of the seventh to (K + O th, 29, 30 are connected to the recording control inputs from the first to K-hiA analog storage elements 31.32 (AZE1, AZEK, respectively). The device also contains a source of reference voltage 33 (IEN1 ), integrating capacitor 34, resistive voltage divider 35, formed by series-connected resistors 37,., 38, having a second reference terminal 39, outputs 40 ,,. 41, adjustable voltage source 42, operational amplifier 43 (OU), seventh switch 44, the eighth switch 45, the fifth analog switch .46s second source the reference voltage 47 (IEN2), the third source of the reference voltage 48 (IENZ), an additional analog memorize the pg element 49 (AZE), the first 50 and the second 51 matching resistors.

 As a synchronization unit 8, a single-chip microcomputer of type KM1816BE48 can be used, whose outputs nopvoB form the corresponding outputs and output groups of block 8, and the output can be the analyzed microcomputer input.

The device works as follows. I.

When processing any input signal, post it, into the operational amplifier via the second 55 or third 56 analog inputs (for example, when integrating the input current signal through the second analog input of the device 55, for which the keys 15,16 and 19 are closed, and analog switch 21 is configured to transmit a signal from an additional signal input to the input of amplifier 43), the signal from the first analog input 57 can be entered and stored in the device, for which switch 22 is configured to transmit a signal from input 57 to output, and yes Next, the input signal is fed to the input of the storage element 49, in which it can be stored by the corresponding control signal from output 54 of block 8. After integrating the input current signal from input 55 and storing the result in one of the elements 31 ... 32, the input signal ( sampling it from element 49 can be read through the first input of analog switch 46 and resistor 50 through appropriately configured switch 21 to input of amplifier 43 for further processing — for example, for comparison with a set of

35

The signals produced in multiplier 25 ensure that the resistor is switched on by the converter 4 when connected to its input 5 of the source of the reference voltage 33 — i.e. when implemented using converter 4, amplifier 43 and comparator 3 (with the first input connected via a properly configured switch 24, to the zero potential bus, and the second input connected via a closed switch 45, to the output of the amplifier 43) of any analog algorithm - digital conversion.

Simultaneous addition of three signals in the device is performed as follows. One of the signals iiocT.y- passes through the appropriately configured switch 23 from the output of any storage element 31 ... 32 or the source of the reference voltage 33, the second from the output of the switch 22 through the closed switch 44 from the source of the regulated voltage 42, either from the first analog input of the device, or from one of the M analog storage elements. The third signal can be received through the switch 46 and the resistor 50 from the source of the reference voltage 48 or element 49. The signals are summed as the corresponding currents) at the analog output of the converter 4 and through the additional signal input of the appropriately configured switch 21 are fed to the inverter connection of the converter 4 into the negative feedback circuit of the amplifier 43 together with one of the elements 31 ... 32, which, in turn, reduces the intrinsic errors of the storage elements to the errors of Ithel 43. In this mode, the switch 21 is tuned to the transmission of the total current signal 7 output from the converter 4 through its additional input to the inverting input of amplifier 43, whose input is neinverti- rloashy through the closed switch 16 is connected to the bus zero

40 potential.

When the key 45 is open, the comparator 3 allows comparing any signal arriving at one of the inputs dc of the appropriately configured switch 24 with the zero potential coming through the resistor 51 to the second input of the comparator 3. When the key 45 is closed, the comparator 3 allows to receive information about the ratio the signal at the output of amplifier 43 with the levels of any signals that go to the switch 24: from inputs 55 and 56, from source 47, from source 33, from the AE, with the level of zero potential. Since in the code of the amplifier 43 with the appropriate configuration of the device (the output of the switch 23 is connected to the output of the source

50

55

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The input of the amplifier 43, using the capacitor 34 (switch 19) closed in the negative feedback circuit, integrates the sum of the indicated current signals (the switch 16 must be closed and thus the noninverting input of amplifier 43 is connected

10 to the tire of zero potential). With a fixed integration time, the result is proportional to the sum of the three current signals (if they do not vary with time). It is also possible

15 direct addition of the input current signal coming through the closed key 15 to the inverting input of the amplifier 43, with the sum of signals (also current) received at the output 20 and 7 of the converter 4 from the signals from the output of the switch 23, from the output of the switch 22 (via a closed key 44), from the output of the switch 46, the switch 22 and the key 44

ensure the inclusion of a resistor

of the transmitter 4 to the negative feedback circuit of the amplifier 43 together with one of the elements 31 ... 32, which, in turn, reduces the intrinsic errors of the storage elements to the errors of the amplifier 43. In this mode, the switch 21 adjusts to transmitting the total current signal from the output 7 of the converter 4 through its auxiliary input to the inverting input of the amplifier 43, the non-inverted input of which is connected to the zero bus via a closed key 16

potential.

When the key 45 is open, the comparator 3 allows you to compare any signal received at one of the inputs of a properly configured switch 24 with a zero potential coming through the resistor 51 to the second input of the comparator 3. With the key 45 closed, the comparator 3 allows you to receive information about the signal ratio at the output of the amplifier 43 with the levels of any signals that go to the switch 24: from inputs 55 and 56, from source 47, from source 33, from AZE, with a level of zero potential. Since in the code of the amplifier 43 with the appropriate configuration of the device (the output of the switch 23 is connected to the output of the source

33, switch 46 output to source 48 output, switch 21 output to auxiliary input, closed switches 44 and 16, connecting the output of amplifier 43 through switch 22 from keys 44 (any; voltage level with a known resolution is obtained (in the specified mode the device operates as a conventional code-voltage converter), the input signals5 coming to inputs 55 and 56 can be compared with such levels without inputting them and processing in an operational amplifier (for this switch 24 is configured so that the input of comparator 3 is the corresponding input signal was given, and the key 45 is closed.) If sources 33 and 47 do not allow the maximum and minimum levels of signals possible in the device, supplying them to the first input of the comparator 3 through the switch 24 allows you to compare the signal at the output of the amplifier 43 with the maximum possible values (key 45 is closed). The comparison signal in digital form is generated at the output of comparator 3 and is fed to the comparison input of register 1 and the input of block 8, which can carry out its analysis by the corresponding means. and may be used in subsequent operation of the program unit 8,

If during the operation of the device the information entered by the operator (for example, in the form of voltage levels) is to be used, then at appropriate times, the output of the operator-controlled source of adjustable direction 42 is connected via a properly configured switch 22 and the closed switch 44 to the free output of the reverse resistor connection 6 of the multiplying converter 4 and, thus, proportional to the level given by the adjustable voltage source, a current signal is generated at the output 7 of the converter Opel 4. This signal can be used in further operation of the device, as well as any other signals generated at output 1. For example, this signal can be a setpoint in integration processes using a capacitor 34 connected to the negative feedback circuit of amplifier 43 as described above modes. The specified setting will determine the rate of change of voltage at the output of the amplifier 43.

Other modes of operation of the device are also possible, also providing a higher performance per unit of hardware. costs

Claims (1)

Invention Formula A recursive computing device containing a reproducing digital-to-analog converter connected by digital inputs to the bits of the register of bit balancing connected by the input Comparison with the comparator output, digital information input-output with the digital input-output of the device, and control of the input with the first group of outputs of the synchronization unit, connected by the second, third, fourth and fifth groups of outputs to the groups of control inputs of the first, second, third and fourth analog switches, respectively, and the first through sixth exit W - with the control input of the first, second, third, fourth, fifth, and sixth keys, respectively, a group of To analog storage elements, the outputs of which are analog output devices, and the write control inputs are connected to the outputs of the synchronization block from the seventh to (6+ + k) -th, respectively, resistive voltage divider, connected the first reference point to the zero potential bus, and the second reference output and outputs to the signal inputs of the first analog switch, connected by the output to the output of the first key and the inverting input of the operational amplifier connected by a non-inverting input to the output of the third key and the signal inputs of the second and sixth keys, and the output; home - to the signal input To analog storage elements of the group, the output of the fifth key and the first signal input of the second analog switch, connected by the second signal input to the first analog input of the device, and the remaining signal inputs to the outputs from the first to Mth (where) analog the storage elements of the group, respectively, with the output of the second key connected to the zero potential bus, and the signal input of the fifth key is connected to the output of the fourth key and the first plate of the integrating capacitor, the second plate of which is connected to the signal input of the fourth key and the output of the positive digital-analog converter the reference voltage connected to the output of the third analog switch connected by the nepBbLM signal input to the output of the first reference voltage source, and the rest Signal inputs to the outputs from the first to the Kth analog storage elements of the group, respectively, the fourth analog switch connected to the first input of the comparator, the first signal input to the second analog input of the device and the signal input of the first key, the second signal input with the third analog input of the device and the signal input of the third key, and the remaining signal inputs with the outputs from the first to the Kth analog storage elements of the group, respectively, characterized in that in order to improve the performance of the device and expand its area of application by performing summation and comparison operations, it additionally introduced the seventh and eighth keys, the fifth analog torus, the second and third sources of the reference voltage, the source of the controlled voltage, two matching a resistor and an analog storage element, the fourth analog switch being connected to the zero potential bus by the first additional signal input, the second additional signal input to the output Q 5 o 5 Q five five the second source of the reference voltage, the third additional signal input to the output of the sixth key, the output of the additional analog storage element, the additional analog output of the device and the first signal input of the fifth analog switch, and the fourth additional signal input to the output of the first source of the reference voltage the fifth analog switch is connected to the second signal input with the output of the third source of the reference voltage, a group of control inputs from the sixth group ppy outputs of the synchronization unit, and output with the first output of the first matching resistor connected by the second output to the additional fy signal input of the first analog switch and the output of the duplicative analog converter, the feedback resistor of which is connected to the output of the seventh key connected to the free output the signal input to the signal input of the additional analog storage element, the second reference terminal of the resistive voltage divider and the output of the second analogue switch This device is connected to the signal input of the eighth switch, the output of which is connected to the second input of the comparator and the first output of the second terminating resistor connected to the second input to the zero potential bus, and the control inputs the seventh and eighth keys, and the recording control input for the additional analog storage element connected to the first, second and third additional outputs of the synchronization unit, respectively.