SU1520666A1 - Converter of two-decade binary-decimal code to binary code - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of binary-decimal converters. The aim of the invention is to simplify the converter. The goal is achieved by the fact that in the converter of a two-decade binary-decimal code into a binary code containing six-bit 16 and two-bit 17 adders, the fourth bit input of the converter is connected to the transfer input of the six-bit adder and the two-digit adder inputs, the outputs of which are connected to the inputs of the first and second bits of the six-digit adder. 1 il.

Description

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The invention relates to automation and computer technology and can be used in the construction of converters in control, computing, information-measuring-1WH devices.

The aim of the invention is to simplify the converter.

The drawing shows a block diagram of the Converter.

The converter has inputs 1-8, outputs 9-15 and contains six-bit 16 and two-bit 17 adders.

The operation of the converter is based on the identical representation of the two-decade AJSon4HO-7; ecHTH4Horo code by three binary codes, followed by their summation.

Let it be necessary to convert the two-decimal code of the decimal number N.

N ai + 2a5, + 4a3 + 8a + (bi + 2bj- -4b, + 8b4) Y.

The binary-decimal code of the number N is fed to the input of the converter, and the bit is fed to input 1, bit V.G / to input 2, razz.a to input 3, etc. The adders 16 and 17 summarize the following binary codes:

O O, a, j b4bzb 1.b- (b2b4 o - 0000 o

Where

X (

Qj-aj + a4

(2)

The sum of the specified binary codes corresponds to the summation of decimal numbers A, B and C, such that

(+ 2Q + 4Q2 + 8b3 + I6b2i

, + 4b2 + 8b, s + 64b4

..

(3) 45

After simple transformations, taking into account expressions (1) - (3),

. . ; . ; .

Thus, on the.) Output of the converter, a binary equivalent of the decimal number N represented in the binary code of the input code of the converter is formed.

To sum the codes OOb; jb-jQ, j ,, and bi b b4b4b2b, 0, an adder 16 is used, and the Signal a, arrives -no

Q

five

0

five

0

five

0

five

0

five

average output 9 converters l. Further, since the OOOOOO code O contains zeroes in all bits except the second, its summation with the indicated codes can be performed by sending a signal to the transfer input of the adder 16. The values of Q, and Q, j are obtained using the adder 17. At the output adder 16, the transfer signal does not occur with any input binary-decimal codes. Therefore, to obtain QH and Q signals in accordance with expressions (2), it is possible to use free third and fourth digits of a four-bit adder chip, considering them as independent one-digit adders. In binary-decimal input code signals a. and a, af and a cannot simultaneously take the value of a logical unit, since combinations of the numbers IXIX and 11XX (where X is any state, O or) in a binary-decimal code with weights 1, 2, 4, 8 are prohibited. Therefore, when forming signals at the outputs of the adder 17, no transfer signals occur and the adder 17 can be replaced with two OR elements, which leads to a decrease in the converter.

Claims (1)

Invention Formula The converter of a two-decade binary-decimal code into a binary one containing a two-digit adder and a six-digit adder, the outputs of which are the outputs of the higher bits of the converter, the output of the first-order bit of the converter, the inputs of the first digit of the converter the sixth bits of which are respectively connected to the first inputs of the first and second digits of the six-bit adder, the first 8CODES of the fifth and sixth digits of the test-discharge adder are connected to the input of the logical yul In order to simplify the converter, in it the inputs of the second and third bits of the converter are respectively connected: With the first inputs of the first and second bits of a two-bit adder, the outputs of which are connected to the second inputs of the first and second times - It is a shtyrazdrazdn adder, the transfer of which is connected to 51520666 the input of the fourth bit of the conversion of a styrene adder, the second input and with the second inputs of the first year of the third and fifth bits of which two and two bits of the two cohorts are connected to the input of the seventh distributor, the inputs of the fifth and sixth converter, the input The eighth bit of the converter of the corresponding bit of which is connected to the second is connected to the first inputs of the fourth and sixth bits to the third and fourth bits of the six-bit adder.