SU1520592A1 - Storage - Google Patents

Abstract

The invention relates to computing and can be used in the construction of large storage devices. The purpose of the invention is to increase the information capacity of the device. The storage device contains two address registers, device address inputs, its memory archive block, two comparison blocks, device information outputs, word register, code memory block, code register, input register, device information inputs, four switches, auxiliary register, register free cell, counter, AND block, adder, shift register, write, read, reset inputs and overflow signal output, device sync input. 1 tab., 4 Il.

Description

The invention relates to computing and can be used in the construction of large storage devices.

The purpose of the invention is to increase the information capacity of the device.

The figure shows a block diagram of a memory device; Fig. 2 is a block diagram of one of the variants of the control unit; Fig. 3 is a flowchart of the control unit operation in the read mode; Figures 4 through 6 are a flowchart of the operation of the block, the control in recording mode.

The storage device has (FIG. 1) the first address register 1, the address inputs 2, the first output 3 of the block

4 controls, archive storage unit 5, second 6 and third 7 outputs of the control unit, first comparison block 8, first 9 and second 10 inputs of the control block, information outputs 11, register of 12 words, fourth 13 and fifth of the 14 outputs of the control block , information inputs 15 of block 16 of code memory, register 17 of codes, sixth 18 and seventh 19 outputs of control block, second register -20 addresses, eighth 21, ninth 22, tenth 23 and eleventh 24 outputs of control block, input register 25, information inputs 26, the first 27 switch, the twelfth output 28 of the control unit, output d 29 code memory block, second 30 and third 31 commutasd

CD 01

with to

tori, auxiliary register 32, fourth switch 33, free cell register 34, thirteenth 35 and fourteen} 36 outputs of control unit, counter 37, fifteenth 38, sixteenth 39, seventeenth 40 and eighteenth 41 outputs of control unit, second comparison unit 42, unit elements 43, the adder 44, the shift register 45, the nineteenth 46, the twentieth 47, the twenty-first 48, the twenty-second 49 and the twenty-third 50 outputs of the control unit, the third input 51 of the control unit, the write entries 52, read 53 and set 54 to the original status, signal input 55, output 56 block overflow, control and twenty-fourth exit 57 control block

The control unit () has a synchronization input 58 of the device, a block 59 of the permanent memory of microprograms, a register 60 of microcommands, a counter 61 of the address and a block 62 of multiplexers O

The operation of the device is based on the fact that each memorized word is associated with its code, which has a smaller size than the word itself. A shorter code is written instead of a word at the appropriate address in block 5 of the archive memory, which allows increasing the information capacity of the device.

All memorized words and their codes are stored in block 16 of the code memory, whose cell in the first group of bits stores one memorized word, and in the second group of bits the corresponding code. When the system is loaded, words (and their codes) are placed in block 16 memory codes in order of increasing, which allows for binary search. The address of the first non-access cell of the code memory block 16 is entered into the free cell register 34. If a word is memorized for the first time, it is entered in block 16 of the code memory and supplied with a code that is equal to the arithmetic mean of the codes in the neighboring cells.

The device works as follows

Dp of preparing the device for operation at the input 54 of the control unit 4 is given a pulse, which sets it to the initial state. After that, the input 53 (52) of the control unit 4

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a signal is received that translates it into a read-out mode of recording information, and an address code is fed to the address input 2 of the device, at which information must be read (written) on

When the control unit 4 is operating in the read mode (Fig. 3), each block (except for the condition test) describes the state of the outputs of the control unit 4 during one clock period. C (...) is the signal at the corresponding input-output. The flow diagrams of FIGURES - 6 show signals having logical I values. The signals not shown in the blocks over the corresponding clock period are assumed to be zero.

In the first clock period (block 1, fig. 3), the address of the information to be linked is recorded in register 1 (C (3) 1) and fed to the address input of memory block 5, which is switched to read mode by the output 6 of control block 4 due to From the information output of the memory block 5, the code of the word to be counted is fed to the first input of the comparison block 8. The output of register 12 is transferred to the high-resistance state by signal C (14) 1. At the same time, register 32 is reset (C (40) 1). In addition, from the output of register 34 through the second input of the switch 33 (since C (36) 0, the number 37 is copied to the counter 37 (C (38)) the number that is the address of the first free cell of the memory block 16 received at the second input of the adder 44 , the first input of which is the code of the number 0. The code of the number N from the output of the adder 44 is fed to the information input of the register 45 and is written into it due to 0 (47)

In the next clock cycle (block 2, fig. 3) in register 45, the signal C (48) 1 shifts this code to the right with the loss of the least significant bit and filling the most significant bit with zero. Thus, on the information input of the register 20

code number

.

where's the quad

military brackets mean the integer part of the expression enclosed in them. By signal C (19) 1, this code is entered into register 20 and is fed to the address; the input of the memory block 16, which is switched to read mode by signal C (21) 1. Of

memory block 16 is read, containing N my cells with the address

the code recorded therein from the second group 29J of the output bus 29 bits through the second input of the switch, 27 (since C (28) 0) passes to the second input of the comparison unit 8. If this code

memory device (C (14) 0) "The control unit 4 generates a logical 1 at output 55-, which is supplied to the signal output 55 of the device, signaling the completion of a given operation.

If the device is set to record mode

more code submitted to the first input JQ - information, it works as follows. According to the signal C (52), the operation of the control unit 4 is organized in accordance with the block diagram (FIG. 4). In the first clock period (the block

the comparison unit 8, then a unit is formed at the first output of the latter, fed to the input 9 of the control unit 4. This entails that

shimm way. According to the signal C (52), the 1st block of the control block 4 is organized in accordance with the block diagram (FIG. In the first clock period (block

in the next clock period (block 4,, 5 FIG4) from information input 26

devices in register 25 are entered (C (23) 1) with a written word, which is also rewritten in register 12 (C (13) 1). Simultaneously with the address

Fig. 3) from register 45 through the second input of the switch 31 (C (5) 0) and the first input of the switch 33 (C (36) 1) to the counter 37 is recorded (since

N 1 g I, as a result, the output of the adder 44 forms a code that is written to

register 45 (C (47) 1).

If there is an inverse ratio of the codes at the inputs of comparison unit 8, then a high level signal appears at its second output.

the device in register 25 is entered (C (23) 1) the written word, which is also rewritten in register 12 (C (13) 1). Simultaneously with the address

20 of input 2 in register 1 is entered the address at which the word must be written. At the same time, in the same way as in the mode of the register, the code of the number is written in register 45. AT

25, in the next clock period (block 2, figure 4), the code entered in register 45 is shifted to the right by one bit (C (48) 1) and rewritten into register 20 (C (19) 1), as a result of which

and is fed to the input 10 of block 4 of the control - 30 bdok 16 of the memory is read (C (21) laziness. In this case, in the following so- 1) the contents of the cell with the address of the period (block 6, FIG. 3) the code H1; register output 25

 G N 1t v J

Ate - from the output of the switch 31 is written to register 32 (C (41)). ,

As a result, from the output of the adder 44 to the read mode (C (21) 1), the reactive input of the register 45 is transferred to the high-resistance state (C (24) 1), the memory block 16 goes

As a result, through the first input of the switch 27 (since C (28) 1) to the second input of the comparison unit 8 delivers

3N is given the code of the number -.

After that, the device works as described. In the next (block 2, fig. 3) cycle, the code stored in register 45 is shifted to the right and written to register 20, which causes the contents of the cell 16 of the memory having the address

II

or

t N), and t, Do. Thus, a binary search is performed in block 16 of a cell containing in the second group of its bits a code identical to that read from block 5 of the memory.

both outputs of block 8 are compared with the presence of logical zeros at the output, p.

code extracted from block 5 of memory. After this (block 8, fig.Z) from the output of the register 12, the word passes to the information output 11

dah of the comparison block 8, This results in the next clock period (block 20, fig 4) transferring the memory block 5 to the recording mode (C (7)), as a result of the second

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memory device (C (14) 0) "The control unit 4 generates a logical 1 at output 55-, which is fed to the signal output 55 of the device, signaling the completion of a given operation.

If the device is set to the recording mode - the information it works as follows. According to the signal C (52) 1, the operation of the control unit 4 is organized in accordance with the block diagram (Fig. 4). In the first clock period (block 1,

the device in register 25 is entered (C (23) 1) the written word, which is also rewritten in register 12 (C (13) 1). Simultaneously with the address

the input 2 to the register 1 is entered the address at which the given word should be written. At the same time, the code of the number is written in the register 45 in the same way as in the same way. AT

the next clock period (block 2, figure 4), the code entered in register 45 is shifted to the right by one bit (C (48) 1) and is rewritten into register 20 (C (19) 1), as a result of which

transferred to the high-resistance state (C (24) 1), the memory block 16 goes

in read mode (C (21) 1), in

As a result, through the first input of the switch 27 (since C (28) 1), the contents of the first group of bits of the cell read from the block 16 are fed to the second input of the comparison unit 8. At the first input of the block 8 comparison with the output of the register 12 is supplied the recorded word information output

memory block 5 is in a high-resistance state, since C. Further (blocks 3-7, fig „4), a binary search is carried out in block 16 of a cell containing in its first group its

bits word, identical to the recorded note. The operation of the device in this mode is similar to the operation of blocks 3 - 6 read modes. The time of finding this cell is identified by

 .

dah of the comparison block 8, This results in the next clock period (block 20, fig 4) transferring the memory block 5 to the recording mode (C (7)), as a result of the second.

The group of bits 29j of the bus 29 in the corresponding cell of the memory block 5 is written down the code of the memorized word,. Then (block 21, figure 4) control block 4 forms logical 1 on

output 35, arriving at the signal output 55 of the device, after which the operation of the device ends

However, it is possible that in memory block 16 a cell with a memorized word will not be found, which indicates that this word is memorized for the first time. Then on some n-mare binary search, where n logjN + l3, the situation is reached, in register 32 and the counter 37 is provided with codes of numbers that differ by one (we denote them, respectively, by M and M + 1), then at the output of the adder 44 they have 2M + 1, and at the output

.. G 2M + 1 1 shift register 4j 1 -j-

 m + l m + ul m-i-0 m. v

As a result, the comparison unit 42 forms at its output a unit arriving at the input 51 of the control unit 4. The arrival of this signal indicates the need to shift the contents of the cells of the memory block 16, which have addresses from M + 1 to N-1, one cell ahead and record the new of the word being written into the cell with the address M + 1 together with the code generated for it. Consequently, in the next clock period (block 8, fig 4) from the register 34 through the second input of the switch 33 (C (36) 0) into the counter 37 is written (since C (38) is 1 the code of the number N arriving at the second input one adder 44, the first input of which is fed zero, since C (57)

read the contents of the cell with the given address C of the second group of bits 29j of line 29, the code written into this cell through the first input of the switch 30 C (49) 1 enters the register 17 and is entered into it by the signal C (18) i. The word stored in the extracted cell from the first group of bits 29l of bus 29 is rewritten to register 12 (C (13) 1, and the output of register 25 is in a high resistance state due to C (24) -1. Next (block 13, FIG .4) a unit (C (46) 1) is iodized at the transfer input of the adder 44 15, thanks to which the register 45 records (G (47) l) the cell address of the memory block 16 following the one whose contents is located in registers 12 and 1 7. Further (block 14, figure 4) this address is recorded in register 20 (C (19) -1), and then supplied to the address input of memory block 16 transferred to recording mode by signal C ( 22) 1. In p As a result, the contents of registers 12 and 17 are written into the appropriate cell. The cyclic operation of control unit 4: working units 10-14 (Fig. 4) allows the contents of cells of memory 16 to be moved one cell forward. until after the next reduction of the contents of the counter 37, the number M. B appears in the latter, the result is that the codes at the inputs of the comparison unit 42 become equal and it supplies the logical I to the input 51 of the control unit 4. After receiving this signal (block 15, figure 4) from memory block 16, the contents of the cell with address M are extracted (C (21) 1). From the second group of bits 29i of bus 29, the code recorded in this cell is through the second input of switch 27 ( block 17, fig 4)

b0 „. from output 46 of control unit 4

to the transfer input of the adder 44 delivers - 5 C (28) 0 and the first input of the switch

with unit As a result, register 31 (C (50) 1) is written (C (41) "1)

45 record (C (47)) N + 1 o In the next clock period (block 9,) this number is written (0 (35)

50

1) in register 34. Next (block 10, FIG. 4), the contents of counter 37 are reduced by one (C (39) 1) and unchanged (C (39) 1) and (C (46.48) "0) to register 45 (С (47) 1), and then to register 20 (С (19) 1 to the block through the second input of the switch .27 ке 12 (fig4)) This address gives (С (28)), the first input switch to the address input of the memory block 16, 31 (C (50) 1) and the first input of the switch-switched to the readout mode of the signal 33 (C (36) .- 1) is rewritten (C (38) with C (21 ) 1. From block 16 of memory 1) to counter 37 and fed to the head register 32. Next (block 16, fig 4) the presence of C (46) 1 ensures the formation of o adder 44 code of the number M + 1, which is stored (C (19) 1) in register 20 (block 17, fig 4). As a result, the contents of the cell with this address are read from memory block J6.

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read the contents of the cell with the given address C of the second group of bits 29j of line 29, the code written into this cell through the first input of the switch 30 C (49) 1 enters the register 17 and is entered into it by the signal C (18) i. The word stored in the extracted cell from the first group of bits 29l of bus 29 is rewritten to register 12 (C (13) 1, and the output of register 25 is in a high resistance state due to C (24) -1. Next (block 13, FIG .4) the unit (C (46) 1) is iodized at the transfer input of the adder 44 5, thanks to which the register 45 records (G (47) l) the cell address of the memory block 16 following the one whose contents is located in registers 12 and 1 7. Further (block 14, figure 4) this address is recorded in register 20 (C (19) -1), and then supplied to the address input of memory block 16 transferred to recording mode by signal C ( 22) 1. In p As a result, the contents of registers 12 and 17 are written into the appropriate cell. The cyclic operation of control unit 4: working units 10-14 (Fig. 4) allows the contents of cells of memory 16 to be moved one cell forward. until after the next reduction of the contents of the counter 37, the number M. B appears in the latter, the result is that the codes at the inputs of the comparison unit 42 become equal and it supplies the logical I to the input 51 of the control unit 4. After receiving this signal (block 15, figure 4) from memory block 16, the contents of the cell with address M are extracted (C (21) 1). From the second group of bits 29i of bus 29, the code recorded in this cell is through the second input of switch 27 ( block 17, fig 4)

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the code through the second input of the switch .27 (C (28)), the first input of the switch 31 (C (50) 1) and the first input of the switch 33 (C (36) .- 1) are rewritten (C (38) 1) to the counter 37 and feeds into the register 32. Next (block 16, fig. 4) the presence of C (46) 1 ensures the formation at the output of the adder 44 of the code of the number M + 1, which is stored (C (19) 1) in register 20 (block 17, fig. 4) o As a result, the contents of the cell with this address are recorded from memory block J6.

44, at the first input, the contents of the reyra input of the adder which receives the gistra 32 (since C (57) 1). As a result, p register 45 is recorded (C (47) 1) the sum of the codes stored in the cells of memory 16 with addresses M and M + 1O Next (block 18, figure 4) the signal (C (48) 1) provides the offset this amount one bit to the right. The resulting arithmetic average of the codes through the second input of the switch 30 C (49) 0 is written to register 17 (C (18) 1) and from its output goes to the second group of bits 15 of information input 15 of memory 16, which is in recording mode C (22) 1 in block 21 (FIG. 4) o On the first group 15i | The bits of the information input 15 of the memory block 16 through the register 12 0 (13), C (14) 0 from the output of the register 25 are fed the memorized word. As a result, the memorized word is written into the cell of the memory block 16. with his code. Thereafter (block 20, fig. 4) the memory block 16 is translated into the read mode C (21) 1 and the device operates as described.

It is possible that the codes stored in the cells of the memory block 16 with the addresses M and M + 1 differ by only one unit. Then, after calculating the arithmetic average of the codes (block 19, fig-4), due to the loss of the fractional part of the shift, the codes at the inputs of the comparison block 42 are equal. According to the signal C (51) 1 generated at its output, the control unit 4 forms (block 25,) at its output 56 a unit arriving at the output 56 of the overflow device. This signal causes a system reboot with the redistribution of codes to provide the necessary intervals between adjacent codes in block 16 of the code memory.

Operation of the storage device in the recording mode Let the storage device write the binary 20-bit words from the set shown in the table

Each word is equipped with a 6-bit code. This loading table is loaded into the first 10 cells of the block 16 of code memory when loading. When writing the word 00000000000110011111 in the process of binary search, it is found that

its word is written in the first group of bits of the second cell of the code memory block 16. Then, from the second group of bits of the given cell, the corresponding code 001000 is found and is written into block 5 of the archive memory at the specified address.

Consider the case when the word is memorized for the first time. Let the word 0000000001000000000K be recorded. After the search is completed, it is clear that there is no such word in block 16 of the code memory. Since the meaning of this word is greater than the value of the word written in the fourth cell, and less than that located in the fifth, this word must be written in block 16 of the code memory between these words. For this, the contents of 5-1 to 10th cells of block 16 are moved one cell forward, and the recorded word is entered into the 5th cell. In accordance with it, a code becomes equal to the arithmetic mean of codes of adjacent words, namely, 010010. This code is stored in the second group of digits of the fourth cell, as well as in block 5 of the archive memory at the specified address.

formula of invention

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The storage device containing the input register, the first address register, the first and second comparison blocks, the counter, the information inputs of the input register are information inputs of the device, characterized in that, in order to increase the information capacity of the device, an adder is entered into it, the first is a quarter switch -m, control block, code memory block, archive memory block, second address register, free cell register, auxiliary register, shift register, code register, word register, and block of elements AND The array inputs of the QQ memory block are connected to the outputs of the first address register, whose information inputs are the address inputs of the device; the first and second outputs of the first comparison block are connected to the first and second inputs of the control unit mode set; the outputs of the archive memory block are connected with the inputs of the first group of the first comparison block, the outputs of the register of words.

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The information inputs of the first group of the code memory block are the information outputs of the device, the codes of the code register are connected to the information inputs of the second group of the code memory block, the address inputs of which are connected to the outputs of the second address register, whose information inputs are connected to the outputs of the shift register, inputs of the first groups of the second comparison unit, information inputs of the first group of the second and third switches, the information inputs of the second group of which are connected to the outputs of the first the switch and the inputs of the second group of the first comparison unit, the outputs of the input register are connected to the corresponding information inputs of the word register, the outputs of the first group of the code memory block and the information inputs of the first group of the first switch, the information inputs of the second group of which are connected to the corresponding outputs of the second group of the code memory block , information inputs of the archive memory block and information inputs of the second group of the second switch, the outputs of which,. connected to the inputs of the register of codes, informational inputs of the shifting register are connected to the codes of the adder, the inputs of the first group of which are connected to the corresponding outputs of the counter, the inputs of the second group c 1 of the matrix are connected to the outputs of the I block, the first inputs of which are connected to the outputs of the auxiliary register and the inputs of the second group of the second block comparison, the outputs of the third switch are connected to the information inputs of the auxiliary register and the free cell register and the information inputs of the first group the fourth switch, the information inputs of the first group of the fourth switch, the information inputs of the second group of which are connected to the outputs of the free cell register, the outputs of the fourth switch are connected to the information

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the counter inputs, the output of the second comparison unit is connected to the third input of the control unit mode, the write and read inputs of which are the corresponding inputs of the device, the reset input and the synchronization input of the control unit are the corresponding inputs of the device, the first output of the control unit connected to the synchronization input of the first register, second and third. outputs - respectively with the read and write inputs of the archive memory block, the fourth and fifth outputs - respectively with the synchronization input and setting the word register mode, the sixth output - with the synchronization input of the code register, the seventh output - with the synchronization input of the second address register, the eighth and ninth outputs, respectively, with the read and write inputs of the code block, the tenth and eleventh outputs, respectively, with the synchronization inputs and setting the input register mode to the twelfth output - with the control input of the first k F1utator, the thirteen output - with the synchronization input of the free zone register, the fourteen output - with the control input of the fourth switch, The first and sixteenth outputs - respectively, with the inputs of the initial installation of the synchronization of the counter, the seventeenth and eighteenth outputs - respectively with the setup input to the initial state and synchronization of the auxiliary register, the nineteenth output with the input of the adder, the twenty and twenty-first outputs - with the synchronization inputs and the shift register, the twenty-second output - with the control input of the second switch, the twenty-third output - with the control input of the third switch, twenty-fourth and two dtsat fifth outputs are respectively first and second control outputs of the device, the twenty-sixth output control unit is connected to the second unit E Rin oda- elements I.

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910515153

Figg

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(end of FIG. B

Claims (1)

A storage device containing an input register, a first register of addresses, first and second comparison blocks, a counter, information inputs of an input register are information inputs of a device, characterized in that, in order to increase the information capacity of the device, an adder is inserted into it, the first and fourth commutators -i ry, control unit, code memory block, archive memory block, second address register, free cell register, auxiliary register, shift register, code register, word register and block of elements AND, address the input inputs of the archive memory block are connected to the outputs of the first address register, the information inputs of which are the address inputs of the device ·, the first and second outputs of the first comparison unit are connected to the first and second inputs of the control unit mode setting, the outputs of the archive memory block are connected to the inputs of the first group of the first block comparisons, the outputs of the word register, the information inputs of the first group of the code memory block are the information outputs of the device, the outputs of the code register are connected to the information inputs and the second group $ of the code memory block, the address inputs of which are connected to the outputs of the second address register, the information inputs of which are connected to the outputs of the shift register, the inputs of the first group of the second comparison unit, the information inputs of the first group of the second and third switches, the information inputs of the second group, g of which connected to the outputs of the first switch and the inputs of the second group of the first comparison unit, the outputs of the input register are connected to the corresponding information inputs 20 of the word register, outputs the first group of the code memory block and the information inputs of the first group of the first switch, the information inputs of the second group of which are connected with the corresponding 25 outputs of the second group of the code memory, the information inputs of the archive memory block and the information inputs of the second group of the second switch, the outputs of which are connected. with the inputs of the code register, the information inputs of the shift register are connected to the outputs of the adder, the inputs of the first group of which are connected to the corresponding outputs of the counter, the inputs are watts A group of adder groups are connected to the outputs of the AND block, the first inputs of which are connected to the outputs of the auxiliary register and the inputs of the second corpse of the second comparison unit, the outputs of the third switch are connected to the information inputs of the auxiliary register and the free cell register and the information inputs of the first groups of the fourth switch, information inputs of the first group of the fourth switch, information inputs of the second group of which are connected to the outputs of the free 5Q cell register, the outputs are of the twisted switch are connected to the information inputs of the counter, the output of the second * comparison unit is connected to the third input of the control unit mode setting, the write and read inputs of which are the corresponding inputs of the device, the installation input to the initial state and the synchronization input of the control unit are the corresponding inputs of the device, the first the output of the control unit is connected to the synchronization input of the first register, the second and third outputs are respectively with the read and write inputs of the archive memory block, the fourth and p the fifth output, respectively, with the synchronization input and setting the word register mode, the sixth output, with the synchronization input of the code register, the seventh output, with the synchronization input of the second address register, the eighth and ninth outputs, respectively, with the read and write inputs of the code block, the tenth and eleventh outputs respectively, with synchronization inputs and setting the input register mode, the twelfth output - with the control input of the first switch, the thirteenth output - with the synchronization input of the free zone register, the fourteenth output - with the input m control of the fourth switch, the fifteenth and sixteenth outputs, respectively .. with inputs of the initial installation of counter synchronization, the seventeenth and eighteenth outputs, respectively, with the installation input in the initial state and synchronization of the auxiliary register, the nineteenth output - with the adder input, the twentieth and twenty-first outputs respectively, with the inputs of synchronization and shift of the shift register, the twenty-second output with the control input of the second switch, the twenty-third output with the control input of the tre fifth switch, twenty-fourth and twenty-fifth outputs are respectively the first and second outputs of the device operation control, the twenty-sixth output of the control unit is connected to the second inputs of the block of elements I.