SU1501260A1 - Series digital filter - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to reduce the sampling rate and simplify the filter. The serial digital filter contains encoder 1, encoder 2, memory blocks and a shift 3 and 4, switch 5, an element of exclusive OR-NOT 6, adders 7, 10, 11 and 12, a decoder 8 and a multiplier 9. The goal is achieved by eliminating multiply and reduce the number of bits needed to represent input samples and weights. 1 dw., 2 tab.

Description

f

G21) 4317037 / 24-09

(22) 10/13/87

(46) 08/15/89. Bul No. 30

(71) Yerevan Polytechnic Institute. Marx and the Leningrad Electrotechnical Institute of Communications. prof. M.A.Bonch-Bruevich

(72) L.M. Goldenberg and R.R. Badal n (53) 681.32 (088.8)

(56) Pogribnoy V.A. Digital Serial Filters with Pulse Code Modulation. Radio engineering, 1984, No. 4, p. 33, fig. 2

(54) SERIAL DIGITAL FILTER

(57) The invention relates to computing. The purpose of the invention is to reduce the sampling rate and simplify the filter. The serial digital filter contains encoder 1, encoder 2, memory blocks and shift 3 and 4, switch 5, element ISKSHO-MOST OR-NOT 6, adders 7, 10, 11 and 12, decoder 8 and multiplier 9. The goal is achieved due to elimination of the multi-bit multiplication and reduction of the number of bits needed for the representation of the input signal samples and weights. 1 dw., 2 tab.

cl

SP

ND

315

The invention relates to computing, in particular to the technique of digital signal processing.

The purpose of the invention is to reduce the sampling rate and simplify by eliminating multi-bit multiplication and reducing the number of bits needed to represent input samples and weights.

The drawing shows a structural electrical circuit of a serial digital filter.

The serial digital filter contains the encoder 1, the encoder 2, the first block of memory and shift (BPS) (M-1) values from the bit binary position numbers 3, the second block of memory and shift (BPS) M values of C-bit binary position numbers and sign bits A, switch 5, element 6 EXCLUSIVE OR NOT, fourth adder 7, decoder 8, mind 9, first, second and third adders 10, 11 and 12.

The proposed sequential digital filter (DF) uses the following filtering algorithm with

use of delta modulation (DM):

N

N. Ic-ti M-1

k.i hci

I

, pt) e (m), (1)

e

de y (N) is the Nth sample of the output 35 signal, represented by the binary position 1-bit code; M is the order of FC with DM; е (nm) is the (pt) -th sample of the quantized continuous step, which is formed when the input signal is converted into a DM signal and is represented by a binary 5-positional b-bit code, and in the case of DF with a linear DM b 1, t, e. the quantization step is constant and is expressed by a one-bit code,

f (t) is the t-th count of the variable quantization step, which is formed when converting the filter weights into a DM sequence and represented by binary-50

zip b-bit code, moreover, in the case of QFs with linear DM, that is, the quantization step is constant and expressed by a one-bit code. It uses delta modulation of enhanced information content (DMPI), which is related to adaptive DM.

The DMCI specificity is the representation of a variable quantization step (n) by a unitary code, and the quantization step itself is variable.

In DMPI, the variable quantization step e (n) changes proportionally to a power of two: c, (n) 2, where, 1, ..., L – H. Represent e (n) as follows:

(n) a „(n). . (n) 2 (2)

io

where a (n) is the coefficient of the sign bit of the nth count

e (n)

a (n) is the i-ro coefficient of the n-th sample of v (n), with a (n), 1. Similarly, imagine

ehn):

Bh

e l (m) with (n) 21c (m), (3) p

where C (t) and Cv, (t) - coefficients,

similar a, (p) and a- (p).

In the case under consideration, when the variable quantization step is expressed by a unitary code, a; (p) and Cu (in) for any values of the pit are different only for one value and r, therefore, from (2.) and (3) we get

e (n) eM)

a (p) -a (p) -2; С „(t) .Su (t) 2.

R

(four)

For a given η the product e (n − mj −e (m), taking into account (4), can be expressed as follows:

% (n-m) -eJ (m) f (n-m) e (p-m) .2 (5)

, 1,. ,, M-1, rf, 1, ... 2b-U;

b (pt) l, (n-m) @ CdSt); (6)

g

 i y

where 5 (n-m) and f (n-m) are coefficients,

similar h, (p), a, (p) and Cg (m), C (m)

Taking into account (5), (6), (7), we remap expression (1) as follows: K1 M-1 21 ZlZfo - (n-m) .2 (8

M. "A. / h

):

k, i Пг1 mmO

From (5), (6), (7) it follows that to determine the product e (nm) 6 (ha), it is sufficient to determine the sign bit ratio in accordance with (6) and the value of the non-zero bit g in accordance with ( 7). Therefore, when performing a convolution in accordance with algorithm (8), the multiplication operation is reborn into a controlled shift operation. It is understood that the product of the unitary codes is also a unitary code, and the unit bit number per product is determined by the sum of the unit bit numbers of the factors.

The unitary code used is a redundant code and, therefore, in order to reduce the size of b, it can be converted to a simple non-redundant code. Decreasing the magnitude of the variable quantization step allows to simplify the construction of blocks of memory and shift. When pre-conversion is used, the weighting coefficients of the DFs are input into the memory block and the shift already in the converted form, and the conversion of the input signal samples is performed at the DF input. Since the sum of non-redundant codes corresponding to e (n-m) and e (i (m)) indicates the number of the unit bit of the product (n-n) - e (0, the conversion to a non-redundant code also makes it possible to simplify the implementation of shift, as shown in the example. Let b 4, for a large class of signals, exactly this value in is optimal,

then e (n-m) and e (ni) without taking into account the sign- X

Only four values listed in Table 1 can take on the discharge bit. Table 1 also shows code combinations of non-redundant codes.

S01

.

U 8)

 5 20

2606

obtained as a result of preliminary transformation - p, (pt),

g. (ha), respectively.

P

The product of e, (n-m) eg (in) can take 2b-1 values indicated in table 2. Table 2 also lists

all possible values of g (n-ni) are P, (n),

,,

where C is the number of bits.

From Table 2 it can be seen that the number of the code combination p, (n-m) + R (m) corresponds to the number of the unit bit of the product e (n-m) e (m). The result obtained is not unacceptable, since the non-redundant code corresponds to the number of unit bits of the factors, and therefore, the sum of the non-blank codes, in accordance with (7), indicates the number of unit bits of the product of factors. In general, the number of bits of a non-redundant code can be determined using the following hyphenation:

()

(9)

where the function defines the nearest largest integer. In the case of DMPI, as a rule, therefore, the value of b can be two or three.

The following designations are given on the block diagram of a serial digital filter:

x (t) - input analog signal j

e (n) is a variable, expressed in L-bit dn1.1M of the binary positioning code, quantization step, formed when the signal x (t) is converted into an LMLP signal; TH (n) —b (n) quantization step transformed into a non-redundant code is variable; and (n) is the sign bit of the variable quantization step 6x (), which is the output signal

p, (w) - pre-transformed into variable-free code variable step kkantopani, corresponding to 1 1st weighting coefficients TF;

Cp (p) is the sign bit of the variable quantization step, which is a DMPI sequence d (pt), the sign bit of the resulting product {y (N) is the output signal expressed by a 1-bit binary position code, memory blocks and the shift should provide storage and shift, respectively, М and (М-1) values С-times of random binary-positional numbers and sign bits.

To implement the product (n-m) e (in), the decryption is used

The rator is about and the fourth address adder 7 connected to it. It uses the fact that a unitary code is generated at the output of the decoder 8, and the number of a single digit is determined by the binary position number supplied to its input.

To build the encoder 2, depending on the value of b, it is necessary to create a table similar to Table 1, And according to it, synthesize a digital combiner,

In the initial state, in BPS 4, weighting coefficients DF P, u (i) are pre-converted into a non-redundant code, with their significant bits C (n) and one zero binary position number, zero binary position numbers are written in BPS 3. The rest of the circuit elements are in a hindered state.

A sequential digital filter operation consists of recirculation cycles of duration T

one

(ten)

Each recirculation cycle is divided into M cycles with a duration T

one

Mf,

(eleven)

At the beginning of each recirculation cycle, in BPS 3, the next, converted in encoder 2, value of variable quantization step gj, (n) and sign bit ad (n), corresponding to the input signal, are entered.

Gabota FC begins with the formation in the encoder 1 of the sign bit) and the variable quantization step (n), which is converted by the encoder 2 into p, (n). In this case, the switch 5 connects the encoder 2 and the encoder 1 to the BPS 3, as a result, the received values of Su (n) and a (n) are recorded in BPS 3. After writing to the BPS 3, the switch 5, switching, connects the input and output of the BPS 3 to each other, i.e., e, provides its recirculation mode, the Switch 5 retains its state until the new value of the variable quantization step and the sign input signal, i.e. during the whole recirculation cycl-Jta, the BPS 4 constantly operates in the recirculation mode. Simultaneously with the recording in the BPS, 3 p, (p) and) are respectively fed to the fourth adder 7 and element 6, to the second inputs of which from CBE 4 are received a variable quantization step g (ha) of the filter weight and the corresponding sign bit C (n ), Formed at the output of the fourth adder 7, the sum g (nm) + g (m) is on the decoder 8. As already noted, the sum of non-redundant codes, indicating the number of unit bits of the unitary codes, simultaneously indicates the number of unit bits at the output decoder 8 therefore output decoder 8 obtain binary positional number nfazhennoe unitary code,

and corresponding to the product e (n-ha) -e (tn). The sign bit (p-g) of the desired work, in accordance with expression (6), is determined using element 6 and

is assigned to the product e () and eKt) by means of the multiplier 9. Note that the multiplier 9 is conditional, since it is used to multiply by plus or minus one. The product taken into account at the output of the multiplier 9, with a sign significant bit, is fed to the first adder 10, in which the constant is performed. Digital summation at the recirculation cycle interval The remaining clock cycles of the recirculation cycle are shifted by one, the information clock recorded in BPS 3

 one

and BPS A and for a given p, when m is changed from O to M, the remaining values of e (n-t)-p (t) are determined. In the end

Xp

for each cycle, the sum received in the first adder 10 is transmitted to the second adder 11, the first adder 10 is zeroed. For a given p with m 0,1, ... M, all M values of the product of (n, m) -e (t) are determined during the last M recirculation cycles. At the moment of introducing the variable quantization step e (n + M-1), the value of the variable quantization step e (n) is lost. The presence in BPS 4 of an additional binary position number ensures uninterrupted operation of the FC, i.e. at the moment of inputting the next value of g (n) in BPS 3 in BPS 4, the zero binary position number is overwritten. The second and third adders 11 and 12 realize a constant digital summation in accordance with algorithm 1. At the output of the third adder 12, an output signal y (N) is formed, expressed by a binary-positional 1-bit code and having a sampling frequency equal to the sampling frequency of the DMPI signal .

From this it follows that the encoder 1, the encoder 2, the second and third adders 11 and 12 are clocked with the sampling frequency of the DMPI signal, and the remaining nodes are clocked with the frequency f. M ".

- b

Claims (1)

Invention Formula A serial digital filter containing an encoder whose input is an input of a serial digital filter, a switch, the first input of which bit is connected to the output of a character bit of the encoder, the first memory block and offset M and (K-1) C-bit values d binary positions, where M is the order of the digital filter, the output of the sign and information bits of which is connected to the second inlet 0126010 the house of the same bits of the switch, the output of the information bits of which is connected to the input of the information bits of the first memory block and the shift M and (M-1) values of the C-bit binary position numbers, the second memory block and shift M and (M-1) values of C-bit binary position-10 numbers, the outputs of information bits of which are connected to its inputs of information bits, the element EXCLUSIVE OR NONE, the first input of which is connected to the output 15 of sign switch switch and the input of the sign bit of the first memory block and cd Yoke M and (M-1) values of the S-bit binary numbers position, and the second input member 20 EXCLUSIVE OR NOT connected to the input and the output of the sign bit of the second memory block and the shift M and (M-1) of the C-bit value of the binary position numbers, and sequentially 25 connected first, second and third adders, the output of the last of which is a serial digital filter output, characterized in that, for 30 reduce the sampling rate and simplify it by eliminating multi-bit multiplication and reducing the number of bits needed to represent the input samples. 35 signals and weighting coefficients, an encoder included between the output of the information bits of the encoder and the first input of the information bits of the switch, and a successively connected fourth adder, decoder and multiplier, the output of which is connected to the input of the first adder, send the first and second inputs of the fourth adder are connected 45 with the outputs of the information bits of the switch and the second memory block and the shift K and (M-1) values of C-bit binary position numbers, respectively, and the second input multiply 0 l is connected to the output of the EXCLUSIVE I.PI-NOT element. Editor M.Tovtin Compiled by S. Muzychuk Tehred M. Khodanych Order 4890/55 Circulation 88A VNII11I State Committee for Inventions and Discoveries at the USSR GK11T 113035, Moscow, Zh-35, 4/5 Raushsk Nab. Production and publishing plant Patent, Uzhgorod, st. Gagarin, 101 table 2 Proofreader T.Paly Subscription