SU1501058A1 - Arrangement for access to dynamic associative data base - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor computing systems focused on associative data stream processing. The purpose of the invention is to expand the scope of application by providing simultaneous access of processors to the database with the ability to update its contents. The device contains memory blocks consisting of shift registers and a group of AND elements, a group of communication nodes, each of which includes two groups of AND elements, a register, an OR-NOT element, a group of OR elements and an OR element. In addition, the device contains a processor readiness register, a mask register, an AND element and a clock, three delay elements. The device provides simultaneous access of processors to the moved database with the possibility of updating information in it. Each processor is connected to a database located in memory blocks, the number of which corresponds to the number of processors, is made using the same communication nodes. The management of the recording of information in the database is performed by means of the mask register and the processor readiness register. The data in the database is moved under the influence of the shift pulses in the shift registers of the memory blocks forming the ring structure. 1 il.

Description

The invention relates to computing and can be used in multiprocessor computing systems focused on associative thread processing.

data.

The purpose of the invention is to expand the ob-; Application areas due to the simultaneous access of processors to the database with the possibility of updating its contents.

The drawing shows a block diagram of the device.

The device contains 1 memory blocks, each of which includes a group of shift registers 2 and a group of IZ elements, 4 communication nodes, each of which consists of an IPI-NE 5 element, And 6 and 7 element groups, and a WIT element group 8, register 9 and item 10, as well as a group of elements And 11, elements 12-14 delay.

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element And 15, trigger 16, generator

17 pulses, mask register 18, processor readiness register 19, device start input 20, device stop input 21, device code inputs 22, device processor readiness 23, device code outputs 24, device information outputs 25, device information inputs 26, outputs 27 knots

4, the inputs 28 of the block 1, the inputs 29 of the blocks 1, the inputs 30 of the blocks 1, the inputs 31 of the nodes 4, the outputs of the 32 nodes 4, the inputs 33 of the nodes 4, the second synchronization control input 34 of the device, the inputs 35 of the nodes 4 and the signal output of the device.

The initial state of the device is characterized by the fact that the registers of the 2 memory blocks 1, the trigger 16, the registers

18 and 19 are set to the O state. At the inputs 34, unit signal levels are set.

A distinctive feature of a computer with a stream data structure is the use of the principle of associative (non-address) search for the required information. With continuous processing of the incoming data stream and transferring the results back to the mainline, this stream is a circulating dynamic database. Moreover, it should contain the necessary elements that ensure continuous and simultaneous access by processors in order to update it.

The proposed device is a buffer memory divided into blocks 1 by the number of processors in the sensitization system and closed in a ring. In this case, each memory block 1 is executed on the shift registers 2, the number of which is determined by the width of the associative data, and the size is selected on the basis of the required capacity of the buffer super-fast memory of the processor. Reception of information

in each memory block 1 is produced

o in the first. registers of all registers 2

shear. The movement of data in memory block 1 is performed by a simultaneous shift in all registers 2, and the data is transferred from the last bits of all shift registers 2.

The information from the outputs of the memory block 1 is fed to the outputs 25 to the corresponding processors, in which it is analyzed by an associative feature and, if necessary, used in the processing.

Communication on the transfer of information to a dynamic database of processors is carried out on inputs 26 with the assistance of communication node 4. This node is the port cd of this processor, through which either the old information from the outputs of memory block 1 is transmitted or re-entered from the processor side. Information transfer control is performed when there is a processor readiness signal to issue data and allow access to the database. At the same time, information is recorded in the first free memory location.

The circulation of data in the buffer memory is provided by switching the outputs of the last node 4 with the inputs of the first memory block 1 and under the influence of a shift pulse simultaneously arriving at the inputs 29 of all the memory blocks 1.

The device works as follows.

Dynamic database management can be assigned to any of the processors connected to the device. From this processor, inputs 20 and 21 give start and stop signals to the device, and inputs

22- mask to register 18. At the same time, the single value of the mask bit permits the write access to the corresponding processor. Single output signals from the zero outputs of the readiness register 19 signify the fulfillment of an exchange request. These signals in the respective processors, when there is information prepared for the exchange, generate readiness signals arriving at the inputs.

23 in the corresponding register bits 19.

Let the buffer memory be in the zero state, in register 19 signals of readiness for exchange from all processors are fixed, and in register 18 of the mask the code 10 ... 00 is set, allowing recording of information from the first processor.

Since the registers 2 are in the zero state, at the output of the OR-NOT 5 element of the node 4,) a single signal is formed, which is open

elements AND 7 through the third inputs, since the first bits of the registers 18 and 19 are in single states, then element 11, is open, and a single signal from its output along the first inputs opens elements 7 at node 4

A start pulse is applied to the input 20, by which the trigger 16 is set to the single state. In this case, the 15 element and 15 and the 3 elements in all memory blocks 1 are opened from the single output of the trigger 16. registers 2. A generator pulse 17, passing through the open element 15, is fed to the input 35 and is used in the processors as a synchronization signal, and in the device at each communication node 4 sets registers 9 to 0.

After a certain delay time, determined by the delay element 14 and equal to the time taken to decide "to remove the signal from the input 34, delayed by the generator 17 on the input 33

information is transmitted from inputs 261 of node 4i through open elements I7 and elements OR 8 to register 9. Simultaneously through the element OR 10, a single signal arrives; to output 32 of node 4 and further to zero input of the first bit of register 19, the latter is set to zero condition. A single signal from the zero output of the first bit of the register 19 is fed to the correspondence of the output 24 and further to the first processor. In this processor, in the presence of information ready for the exchange of a word, a readiness signal is generated that arrives at the installation input into the first 1 register of the register 19. After some time delay, determined by delay element 13 and equal to the transient time in C 7 (6), OR 8 and register 9, the delayed pulse of the generator 17, which is fed to the inputs 29 of memory 1 blocks, simultaneously shifts information in the shift registers 2 memory 1 blocks. Upon completion of the shift, the additional 1-12 delayed delay of the generator 17 is transmitted by the pulse of the generator 17; data is transferred from register 9 of node 4; to registers 2 through the open elements 3 of block 1, memory.

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Subsequently, by the next pulse of the generator 17, the information is transferred and recorded from any processors ready for exchange with the permission signals from the mask register 18 to the first free cell of the memory block 1.

If there is no need to issue

The Q information from the processor, the write lock from the inputs 26, is produced by the zero signal from the single output of the corresponding register register 18 of the mask. At the same time, information from outputs 5 of the terminals 25 enters through a single signal opened at the first inputs from the input 34 of the element 6 by a pulse from the synchronization input 33 and then through the elements OR 8 into the register 9, and then into registers 2 through the elements 3 of the next block 1 memory

If it is necessary to delete any data from the database, the processors will have, for example, associative

25 signs of this data. If the established signs coincide with the signs

readout data from the outputs 25, the corresponding processor removes a single signal from the input 34,

The first inputs are elements of AND 6 in the same 4 communication node. This blocks the transmission of deleted data through this communication node 4 and the register 9 remains in the zero state. Then a delayed pulse generator 17

 on input 29, data is shifted in all registers of 2 memory blocks I. Thereafter, the delayed pulse of the generator 17 is transmitted to the input 30 of the zero information from the outputs of the register 9 in the first bits of the shift register registers 2 of the memory block 1. Thus, in the next memory block 1, its first cell is in the zero state.

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new information.

If necessary, the redistribution of functions to the processors in the computing system on input 21 is given a stop signal, setting trigger 16 to the zero state, and then the device is brought to its initial state.

Claims (1)

Invention Formula A device for accessing a dynamic database of associative data, containing K memory blocks (K-coli715 the number of processors of the computing system), each of which includes t (t is the size of the dacha) shift registers and a group of AND elements, a group of communication nodes, each of which contains an OR-NOT element, two groups of AND elements, an OR element, and a group elements OR, in addition, the device contains a group of elements AND, the processor readiness register, the single inputs of the bits of which are the signal inputs of the device, the mask register, two delay elements, the trigger, the single and zero inputs of which are the start and stop inputs respectively, the element And and the clock pulse generator, the output of which is connected to the first input of the element And, the second input of which is connected to the single output of the trigger, the single outputs of the bits of the processor readiness register are connected to the first inputs of the same elements of the group, in each memory block These outputs of elements AND groups are connected to the inputs of the bits of the same shift registers, the outputs of the last bits of which are information outputs of the device, which, in order to expand application by providing simultaneous access of processors to the database with the possibility of updating its contents, a third delay element is inserted into it, and a register is entered into each group communication node, the reset input of which is connected to the output of the AND element and the signal output of the device code inputs of which are connected to a group of information inputs of the mask register, each output of which is connected to the second input of the same name AND group, the output of each of which is connected to the first inputs of the AND elements of the first group ppas of the same name communication node of the group, the second input of each element AND the first group at each communication node of the group is connected to the corresponding input of the same name group of information inputs of the device, each input of the Device Sync is connected at the same communication node of the group to the first inputs of with ,. 5 5 0 0 5 0 eight second group, the second input of each element and the second group of each communication node of the group is connected to the output of the last bit of the shift register of the same name of the memory block of the same name, the second inputs of the elements of the second group of communication nodes of the group are connected to the inputs of the element OR NOT This node of the group of communications, the output of the element OR NOT in each node of the group is connected to the third inputs of the elements of the first group and the fourth inputs of the elements of the first group and the third inputs of the elements of the second group of each communication node of the group are connected to .out the first delay element, the outputs of the same elements AND of the first and second groups in each node of the group are connected respectively to the first and second inputs of the same element OR groups of this group of communication nodes. The outputs of the AND elements of the first group in each node of the group are connected to the inputs of the OR element of a given group communication node, the output of the OR element of each group communication node is connected to the reset input of the same name of the processor readiness register, the zero outputs of which bits are the code output group of the device The output element And through the first delay element connected to the input of the second delay element, the output of which is connected to the input of the third delay element, the output of which is connected to the first inputs of the elements And groups of each memory block, the output of the trigger is connected to the second inputs of elements And groups of each block the memory, the third input of each element AND group of each memory block, except the first one, is connected to the output of the same name bit of the register of the previous communication node of the group, the third input of each element AND group of the first block is pa ti connected to the output of the same name discharge register last node communication groups, each node outputs a communication group or groups of elements are connected to the inputs of a register, a shift register shift control input of each memory unit are connected to the output of the second delay element.