SU1499355A1 - Storage with parallel random access to data lines and windows - Google Patents

Abstract

The invention relates to computing and can be used in computer systems with parallel processing of information, as well as as a regeneration memory in half-tone and graphic raster displays. The purpose of the invention is to expand the functionality of the device due to the additional format of the circulation in the form of lines. The goal is achieved by the fact that the device contains a memory block 1, an input data block 2, an output data block 3, a control block 4, an address modification block 5, a group division block 6, a multiplexer blocks 7 and 8. 3 hp ff, 14 ill.

Description

QD 00 SL

cl

31499

The invention relates to computing and can be used in computer systems with parallel processing of information, as well as as a regeneration memory in half-tone and graphic raster displays.

The purpose of the invention is to expand the functionality of the device due to the additional format of calls in the form of

Fig, I shows a block diagram of the device; Fig 2 is a block division block diagram; Fig. 3 is a schematic of the control unit; in fig. 4 shows a fragment of the table of the arrangement of the elements of the memorized array modulo-memory modules for H 16; Fig. 5 shows a multiplexer unit, the switching elements of which are connected according to the n-CUBE network connection rule; Fig. 6 shows the wiring diagram of the control inputs of the multiplexer unit under the Russian control; Fig. 7 illustrates the connection of the control inputs of the multiplexer unit to obtain a linear shift of the input word; Fig. 8 is a fragment of a device comprising a circuit of a multiplexer control unit and a connection of control inputs of an input data unit; FIG. 9 is a diagram of the partitioning of the control inputs of the two rus multiplexers; in fig. 10 - communication, carried out by blocks of input and output data when selecting a string; FIG. I1 — communications performed by blocks of input and output data when sampling a square window; Fig, 12 is a temporary diagram of the operation of the device; Fig. 13 shows a fragment of a device comprising a block circuit, an address modification and a block circuit of a memory; Fig. 14 shows a fragment of a device containing diagrams of a dividing unit into groups, first and second multiplexer units and a memory unit.

The device comprises a memory block 1, an input data block 2, an output data block 3, a control block 4, an address modification block 5, a division into 6 groups, a first 7 and a second 8 multiplexer blocks.

The division unit 6 into r-groups contains (FIG. 2) the first code converter 9, the first multiplexer node 10, the second AND code converter, the second multiplexer node 12 and the third multiplexer node 13.

The control unit 4 comprises (FIG. 3) a first converter of 4 codes, a group of adders 15 modulo two, a second converter of 16 codes and a node 17 of multiplexers,

The address modification block 5 contains (FIG. 13) first to third adders 18-20, first 21 and second 22 registers, first 23 and second 24 multiplexers, first 25 and second 26 modulo-two adders.

A fragment of the allocation table of the elements of the storage array modulo N 16 contains (FIG. 4) the upper left corner of the allocation table dp N 16. The numbers of the 3 cells are the numbers of the memory modules into which the corresponding elements of the memorized array fall. Squares measuring 16x16 elements surrounded by a double line are called fields. 4x4 squares circled in bold are called sections. Bold lines are one row and one square, randomly located on the table, which are considered as examples.

The switching elements of the multiplexer node are connected according to the rule for connecting the n-CBE network. There are 16 inputs and 16 outputs, denoted by the letters V and W, respectively. The lower part shows one switching: element with information inputs and information outputs ,, Depending on the state of control of the signal, the C-inputs switch to the output or directly or cross.

The timed work diagram displays the following signals. The YR signal is a multiplexer control signal in block 7, which for each memory module determines which one. The signal RAS1 or RAS2 is entered into the memory module of the first half of the address. The YC signal is the multiplexer control signal in block 8, which determines which CAS1 or CAS2 signal is written to the memory module of the second half of the address. The signal address indicates how the group of bits of the input address is currently located at the inputs of the memory module.

The multiplexers 23 and 24 are controlled by signals B and B, and, if these signals are equal to zero, then signals from the lower inputs pass to the output.

multiplexer, and if equal to 1, then from the upper inputs.

The MS multiplexers in blocks 7 and 8 pass a lower input signal (RAS2, CAS2) to the output if the control signal (YR or YC) is zero, and the upper one if equal to one. The nodes 10 and 13 1 of the multiplexers are identical in their information links and represent the older p / 2 of the networks of the N-SSE network. Both blocks are designed to perform a dyadic permutation: the third is above the whole word, the fourth is above two groups of bits of the input word. Which group of switching elements is controlled by a code such as code 0 // П, where the sign a // b means that the number a is taken modulo b; Switching to groups is performed by a 12 multiplexer unit (according to Table 6) depending on the state input signals from, about (,

The device is intended for storing two-dimensional arrays of words with the possibility of simultaneous sampling of a group of words representing a window or a fragment of a string rightly located on the array. For simplicity, we assume that all words are one-bit. Transition to the words of greater frequency is accomplished by parallel connection of such devices, and the control unit can be one for all devices. The memory block contains 2 N memory modules with a capacity of 2 bits, where r 2 ta; m 1,2,3, ..., Each module has g / 2 address inputs for which two

   Coordinate I

 Xn,. 1, -Xuii / Address gender by I Address in the field

0

stages, the address bit code, one information input, one information output, the read / write mode selection input and the address entry control inputs (RAS, CAS) are entered.

In order to allow parallel sampling of rows or square windows, it is necessary to arrange the elements of the memorized array so that any data block selected on the array is always located in different memory modules. If this condition is not fulfilled, then for some data block 5 it will appear that two or more elements of the memorized array are located at different addresses in the same memory module and will require several access cycles to retrieve them. In addition to placing the array elements in memory modules, it is necessary to place them in the corresponding cells inside the modules. Overall volume

0

consisting of 2

modules obr

9 bits, there will be V 2 bits. We will consider dvuhmer0

memory 5 5 2

a new storage medium having a square shape and a size of 2 .2,. To assign an arbitrary element on the array, you must specify the U / 2-bit address code of the I and U / 2 coordinates bit code of the address of the Jt coordinate

We divide the entire two-dimensional array into squares of L + N elements, which will be called fields. The field is divided into sections of size n to n elements (Fig. 4). We will write the coordinates of an arbitrary element of the array with one bit word, called the address of the array element :

five

0

Coordinate 3

f (ulj. (i-ii - i n d

Address floor on T Address in the field

The address in the field can also be divided into 45 parts:

, c (p-1, ct p-g

PP

d hii-i I h

The address of the site along the axis I The address of the element on the site along the axis J

The address of the square window and the string of IE elements will be set by the address of the upper left element of the figure. Let us assume that all elements of the section are in different memory chips, but at the same address, which is equal to the address of the section. As an example, we will consider a memory consisting of 16 memory microcircuits. Then r 16;

d hii-i I h

p 4. Total memory capacity is V 2 2 bits. This volume allows you to store an array of 1024 1024 1 bits. Sort of, the string “Buce P” consists of 16 elements and the window will be 4 4 in size (Fig. 4). The address structure of an arbitrary element is as follows:

fn AND C / g ...

Address Address The site address is an element field in the field

plot

The elements of the memorized array are arranged in memory modules in a special way. All elements of the fields are placed equally. Placement in the field is subject to the following rule: the field element with the coordinates I and J is placed in the memory module with the number N: 5

N. (1/2)

© J / N,

N, I, J - binary codes of numbers N,

I and: j; I // h is the modulus of the number I according to the basis of n;

 - shift of bits of code I to the right by p / 2 positions cyclically; f - bitwise operation

modulo two.

J // o

J / a

Since all elements of the section fall into the memory modules with the same address equal to the address of the section, the array element with the coordinates

0/19 ... ", +, / m .t. located in the memory module at

The bits d / j, c (, and c /, / b determine the offset of the address of the figure (line or square) relative to the beginning of the section and are used in the address part of the device for control.

For example, for an element of the field with coordinates I 7, J 13, the memory module number is determined as follows: (1 // n) 2 (77/4) - (3) (OOP) - 1100; J 13 1101; N 1100 + 1101 0001 1, i.e. the array element with these coordinates falls into the first memory module. Such an arrangement of data elements in memory modules specified by the table, in which the numbers indicate the number of the module that stores the corresponding element of the memorized array, is shown in FIG. 3. This allocation table is easily obtained in accordance with the dyadic (modulo 2) permutations rule for rows of all sections, with the order of permutations being defined as J // n (J O, 1, ..., 1023; n 4):

j //,

J // n

... with l (l:

  “...

For example, the numbers highlighted in FIG. 4 line and square elements fall into the memory cells of the module with the following addresses:

(Dp line)

(For square)

In a normal, non-parallel (linear) memory, the same bit in the data bus and the same or several data lines always correspond to a specific bit of any word.

914

in one, memory modules. The data bits when writing and reading do not change their purpose and no emphasis is required on the data. How . can be seen from the allocation table in FIG. D, the same memory module can store data in the memory with parallel and multi-format data access, which, depending on the variant, should be sent to different data bus lines. Therefore, a one-to-one correspondence is pre-determined between the elements of the selected data block and the data bus lines.

Let the number of the line in the data bus. Let us take as the main the order in which for two types of

of patterns (square windows and lines) of a new 20 Russian pair of elements in fours.

Line number dexes will be numbered from left to right and from top to bottom, starting with zero. For example, for N 16

L H 1.3

H h b

Ig ito lii

4i ta f4 -IS for a square window and

Lol, l, l3l4l 5l l, l, l9l, .lttl, 4,4.5

FOR the string. If the elements of a selectable data block fall into memory modules with numbers equal to the data bus line numbers, then such an order of modules in the selectable block is called canonical. When moving a window frame or a row according to the allocation table, the orders that are different from the canonical one are obtained. To restore the order of reading and writing, it is necessary to arrange the data. For this purpose, the device uses blocks 2 and 3 and block 4 of the control.

The switching elements constituting the multiplexer units for data ordering are connected according to the network connection rule (Fig. 5). The lower part shows the basic switching element and two switching states depending on the value

control signal. We will call the inputs and outputs of the switching elements, by which the permutation is carried out, informational. The input of the network is input; with; Noah the vector V v.,, V.j, ..., v, v, which, passing through the switching elements, changes the order of its components in accordance with the control signals.

turn into a vector w w

ten

 So,

that W p (V), where p (V) is a permutation function.

We assume that the indices of the components of the vectors V and W increase from left to right (Fig. 5), Rd of switching elements of the network is called a brown. Network COST9IT of logjN rus, which are numbered in order. If all control signals are switching. Since the elements of the Russ are the same, the network implements dyadic permutations of the input vector. Fig. 6 shows how the control inputs of the switching elements are connected to control the dyadic shifts. In total there are N different dyadic permutations, and the zero rus performs the permutation of elements in pairs, per0

25

35

ZO Q

.

50

the second rus is the fours of the elements in eights, etc. The remaining dyadic permutations are carried out with the joint inclusion of several network masses. Linear cyclic shift type permutations are also easily implemented on the network, while continuous control is no longer enough.

Fig. 7 shows how the control inputs of the switching elements are connected to control the linear cyclic shift. The zero rus, as in the dyadic shift, is controlled by one signal, and the first and subsequent rus are divided into groups: the first rus into two groups (switching elements O, 2, 4, 6, etc., the first group and I, 3, 5, 7, etc., the second group), 2nd Russian into four groups (switching elements O, 4, 8, etc., the first group ,, 5, 9, etc., the second group , 2, 6, 10, etc., the third group and 3, 7, 11, etc., the fourth group. The switching elements of the last russ are controlled separately. A total of N-1 groups are obtained. Thus, in order to control the linear cyclic shift, it is necessary for the n-bit code of the number of shifts to be associated with (N-l) -pa3-a sequential control code that controls the switching elements of all groups. For these purposes, the third code converter 14 is used in the block control unit for data multiplexers (Figs. 3 and 8). The values of the control code for any shift can be obtained directly by

the n-ClIBE network scheme, determining the state of the switching elements for each offset. If we number in order from left to right the control inputs of the listed groups of switching elements and write the values

The table is for right shift. Since the shift is cyclic, it is easy to move from the right shift to the left. A shift to the left by i positions corresponds to a shift to the right by positions. Therefore, if the shift needs to be carried out to the left, the shift code should

Open Company Ltd.OOOOOOOOOOO 000 0000000000000000 001

control signals for each shift, you will get a table. I (for W 16), control code values for the implementation of linear cyclic shifts to the right on the n-USE network on 16 inputs.

Table 1

I. .:

be converted to optional; code-.

For a network that implements linear 40 cyclic shifts, it is still possible to perform dyadic shifts.

The values of the control codes for the implementation of dyadic shifts on the n-CUBE network at 16 inputs are given in Table 2.

table 2

The description of the network control can also be represented by the matrix matrix n / 2, whose elements positionally correspond to the position of the switching elements in the network and determine the values of the control signals for them. Such a matrix gives an intimate idea of the switching of network elements and can be easily obtained from the corresponding control code (Tables 1 and 2). For example, the description of network control when implementing an input sequence shift to the right by 9 elements looks like:

M,

The need to perform various permutations in the ordering of data, due to the fact that the frame covering the N elements of the line or square fragment (window) can be arbitrarily placed.

Continuation of table 2

0

five

0

five

Q

For an arbitrary string it is necessary to perform a permutation composition; the linear shift determined by the offset of the line position relative to the beginning of the reference field by J, and the dyadic shift determined by the offset of I relative to the beginning of the reference section (the reference is the field or section into which the left upper element of the figure falls ), given by its address in the array) ,: This composition is defined as the sum modulo two control codes of the corresponding linear and dyadic shifts. So, if the linear shift is matched by the matrix. sSv Diadny - Mood, sEv control matrix M (CTpt-fM) provides the order of the sequence of elements. the lines on the network are defined as:

(lines) (lines) (lines)

M ,, M w.caa ® M u.so.

Example, consider the sample

highlighted in FIG. 4 lines. Its address is determined by a code (tab. 3). Table 3

15

I in

I

-one

1499355

Address floor of L Address of the site in the field of J I Address of the element on the site of J

The specified line is shifted by 5 positions (“{j, about 0101) in relation to the memory module in which the element 91011 is located

5670123 12 13 14 15 8

Tab. Figure 4 reflects the permutation of a dableable string when reading, which is necessary when writing a string to the memory. For 15, I can implement the inverse permutation in order to properly arrange you (Table 5).

Table3

Memory module About 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Data bus lines (item in line)

789 10 3456 15 О 1

In accordance with the rule of forming the network control, we form the matrix M, edI M, d. Since the row is shifted from the beginning of the field by 5 positions to the right, to restore the order of data, it is necessary to shift them by 5 positions to the left. A shift to the left by 5 positions corresponds to a shift to the right by. 16-5 11 positions. Thus, the input code c (j c ((1011 is complementary to it)) at the output of the converter 14 of codes (Fig. 8) shows the code corresponding to the network control matrix (see Table 1):

M

y hp

The matrix M, j, 3g is formed based on the fact that the line is shifted relative to the beginning of the segment by three positions (o (,, оС "П)). It should be noted that when forming the allocation table in Fig. 4, we used dyadic shifts for groups of

sixteen

beginning of the floor and 3 positions (c / o (, in O to I relative to the beginning of the section. As follows from the allocation table (Fig. 4), the line elements are placed in the following memory modules (Table 4).,

Table 4

And 12 13 14

4 items. Consequently, the total diide shift has a value of 12 (code 1 100) and the corresponding UT matrix) is determined by the table. 2:

 00000000 00000000 11111111 .11111111. Now you can define network management as

(lines)

M

iB.cae

jj 5

0

five

Hot pads) (strekki) (ppvkm)

v m „. ..,,. ,,

ul-sev sj.

eleven

1 o

1111

about 10 1

00010001 1 1 100000. The resulting description of network management reflects the operation of the input network (for recording) and the output network (for reading) (Fig. 10).

When sampling an arbitrarily arranged window, in order to obtain the correct order of elements, it is also necessary to perform a composition of permutations: linear cyclic shifts, multiples of n; linear shifts on 1,2, ..., p-POSITION in groups of n elements constituting the rows of a square fragment (pkna) dyadic permutations to compensate for the dyadic shifts - present in the allocation table. As in the case of row sampling, to control the permutation network, a control matrix is formed in the form

(OKMO.) Fe

My - lsrv® o.cSv Matrix is defined as follows. When the window is displaced relative to the position of the reference area along the J axis, linear shifts of elements occur within the rows (n rows of n elements). Such shifts are performed on n / 2 ms of the permutation network, which are matched by the first

The bits o (, o (ис 11, ,, 11) indicate that the window is shifted relative to the reference area, respectively, by three positions to the right and three positions down. To restore the order of elements, it is necessary to implement compensating shifts. The window shift to the left by the three elements correspond to a cyclic shift within the rows (data elements arriving at the groups of data lines W-1 (0,1,2,3); (4,5,6,7); (8,9,10,11); ( 12,13,14,15)) ONE element to the right, Therefore, the rows O and 1 of the matrix are formed by the control code corresponding to the right shift by 1 bit (Table 1). In this case, only those bits of the control code that are associated with the zero and first network links of the network are considered.

Shifting a window three positions up corresponds to a shift one position down. Since one position in this case corresponds to a whole line, this is equivalent to a cyclic shift to the right by 4 elements. Consequently, lines 2 and 3 of the matrix M ,, d are called by the control code corresponding to the right shift by 4 bits (see Table 1). And in this case, those bits of the control code that are associated with the second and third rus of the network are considered;

Thus, in accordance with; code "/ 1o („ II and of ,, “, 11 with obp / 2 lines (O, 1, ..., p / 2-1). When the window is displaced along axis I, the linear shift occurs by an amount multiple of t ( in accordance with the number of elements in a row. Shifts, multiples of r, are performed on the network by the higher n / 2 rusas, and in the matrix M in the lines correspond n / 2, P / 2 + 1, .., n-1,

Q It follows that the matrix M .ca to control the network when sampling a window is formed for the first n / 2 rows by the window offset relative to the oj opHoro portion of J, and for the last 5/2 rows by the offset by I, for example, the square fragment highlighted in FIG. 4, has an address corresponding to the position of its upper left element (Table 6), Table-6

0

M

five

0

five

0

five

I

Growing to a block of data in the form of a square fragment, the code converter 14 outputs control signals that form the control matrix:

.1 1 1 1 1 1 1 G

lORHql 10101010 V.A.C38 11111111

. 1 1 10000 The dyadic shift value is determined by the position of the reference area in the field along the J coordinate, i.e. bits (o.,. ,, c / f, / 2 of the address code. The placement table implements a one-dimensional, di-; adjective shift for groups of n elements, therefore, the higher n / 2 are used to compensate for the dyadic shift. The network's oldest (n- |) -th rus is controlled by the (n-1) th address bit (o (hi) () th rus - (n-2) m bit (o ((, - d) etc. This is true for all sections. However, an arbitrarily addressed window can be positioned so that it immediately falls on two sections along the J axis. In this case, different dyadnas should be implemented for different parts of the network. shifts. LL of memory modules falling on the reference area, the value of the dyadic shift DS 1 is determined by the bits

DS 1 tf. d ,,, “0/4, and for the next section the code DS2 (, ...,) //

 / n-1 f (n-l

, (

SP

191499355

It is easy to see that there are n variants of combinations of DS1 and D92 when managing parts of the older n / 2 Rus network. They are determined by the magnitude of the displacement of the window relative to the reference portion along J, i.e. The digits to / t-i ,, about the address code. For N 16, the combinations of shifts for the groups of elements of the 2nd and 3rd Rus network are presented in Table. 7, Table

ten

An example of dividing switching elements into groups is shown in Fig. 9, where two older ruses of switching network elements are shown and dividing them into groups to compensate for the dyadic shift when the window falls into two sections.

Control of various groups of switching elements is performed by converter 16 and multiplexer node 17,

Bus lines

data O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Module mod-

m ti 12 14 14 15 O 1 2 11 4 5 67 8 9 10

 I

Table9

Memory module О 1 2 3 4 5 6 7 8 9 10 И 12 13 14 15 --- i 4

LINES LINES

5 6 7 O 9 10 11 12 13 14 15 8 1 2 3 4

Consider the work of the address part of the device. The address part of the device includes the address modification block 5, the block dividing unit 6, the first 7 and second 8 multiplexer blocks, and the address inputs of the memory modules. As follows from the description of the placement of information on the memory modules,

0

five

20

Now it is possible to form a matrix (window; V.

sampling of the window, whose position is set in FIG. 4, the dyadic shift value for memory modules 3, 15, 11, 7 is determined by the size of the address code, i.e. DS1 11, and dp of the remaining elements of the window DS2 (P + 01) // 4 O, In accordance with the code o (, in (and

The type of address (window) of the converter 16 codes provides the control code 1000 to the input of the node 17 multiplexers, the output of which removes the control code of the 2nd and 3rd rus of the network corresponding to the matrix

0

M

(Windows "/

1.G} .SZeG

About About About About

About About About About

LTD

ABOUT

Oh oh

one

one

oh oh oh

oh oh oh

The final permutation control in this example is:

1 1 1

01 Oh

1I 1 000

Such network management ensures the ordering of the elements of the data block (Fig. 11), given in Table 8 (during writing) and 9 (when reading).

Table 8

By sampling an arbitrarily located square, the memory modules can be divided into two groups, the addresses of which along the J axis differ by +1, and by the two groups whose addresses along the axis I also differ by + |. In some memory chips, to reduce the number of address inputs, the full address is

211499355

The selected word is entered in two stages: At first, one half is entered.

to addresses (by RAS signal), and then the second half (by CAS signal). Two signals are input into the device.

enter the first half of the address

(RAS1 and RAS2) and two for the second (CAS and CAS2), These signals are shifted in time relative to each other. For each memory module, two signals from this quad (one from each pair) are switched for one cycle of treatment, depending on the control signals YR and YC generated in the division into groups. Directly switching the signals RAS1 or RAS2 and CAS 1 or CAS2 is carried out respectively by the first and second blocks of the address multiplexers. If, by the RAS1 signal, add the address bits belonging to the J coordinate to a part of the memory modules, then add the +1 bits to this part and add the received address to the remaining memory modules by the RAS2 signal, then after performing a similar operation with entering address bits related to the coordinate I, by signals CAS 1 and CAS2, Tpe6yef ie the addresses will be fully recorded in the memory modules,

The timing diagram of the addressing operation is shown in FIG. 12 The YR and YC signals do not change their value during the recording time; the addresses. The time t, is the address holding time (bits e () is determined from the specific characteristics of the memory chip. The time ti is the time required

to perform the operation add-Q check at the addresses assigned to laziness. + 1 and get the address / o where w / o t +1, The minimum time between the signals RAS1 and RAS2 is equal to the sum of the times t, + t. Analogue Fig. 4 lines, B d a and hell (-

the address of the memory modules includes the following addresses:

the picture also holds for the signals CAS1 and CAS2; tj is the address holding time; t ,. - time of its modification. Thus, by lengthening the memory access cycle by

H × H t4

is provided

50

it is possible to refuse the need to have each accumulator with its own adder. For an operation mode in which the selectable data does not have an offset from the region, it is possible for, d. speeding up the sampling process, reject the four-stroke addressing system, and use the usual push-pull for shortened time dia22

grams The modification of the address (adding +1 to a certain part of the bits and their switching to the address inputs of the memory modules) is performed in block 5 of the address modification. The address inputs of the memory modules are connected to the address bus in a special way,

- - the bit address (where 2 - volume

memory modules) is supplied to the memory modules in the form of three buses Q, X, Y. The section of the bus is Q - - ((where N

-2 - the number of modules used

memory), in this bus are connected in parallel all the higher bits of the address inputs of the memory modules. The width of the tires X and Y is equal to p / 2. Tires X, Y and S are connected in the following way: Y X ® S

or

© S

 n (1 - n (g-1

, ..., Y о Хц / 1-, ®

h / 2-l

Sig-r ® Xh, j.j, ... , Xp® Sj,

where S is the type code of the call.

5 At the same time, the p / 2 low bits of the address of the memory modules are connected to the X and Y buses according to the following rule: if the (n − 1) -th bit in the memory module number is O, then the input of the p / 2-7 module A pair is connected to (p / 2-1) th bus discharge X, t, e. to X f, /.,, and if this bit in the number of the module is 1, then k (n / 2-1) is the bit of the U bus, i.e. .-1, etc. Such a dyadic connection of address inputs allows, when fetching rows, to apply to different groups of n memory modules, addresses that enumerate all values in n / 2 lower bits. This requirement can

five

check the addresses listed on

FIG. 4 lines, B d a and hell (- 2)

the address of the memory modules includes the following addresses:

Number of memory modules 8, 9, 10, 1101

4, 5, 6, 710

O, 1, 2, 311

12, 13, 14, 1500

Thus, if S .11 .., 1, then all addresses in groups are different. With S 00 .., O we get that Y X + 00 ,,. 0 X and in all modules the same addresses. Consider the procedure for entering addresses into memory modules with examples.

A sample of the square with the address 00000011110000001111, highlighted in FIG. 4. Code S in this

23149935524

mode is equal to 00, therefore, the sign-group and entering the address along the J

The address addresses in bits are the same on all modules. Before sampling, the state of the control signals of the multiplexers, which means that the channel is open for the lower (in FIG. 3) busses of the multiplexers 23 and 24, In this state

in two cycles, In this mode, the code S 11, BO O, B | 1 and 1 are added to bit (). Since, when sampling strings, bits "(" - ,, „., ,,,, / h / i accept quite specific values depending on the value of bits / ,, ffio, they are given to rfgrfj 7" 5-4 ee 2 00000011, So on address buses. Therefore, first S 00, then this address will fall without “e“ t fi s 00000011,

changes to all memory modules, t, e,; and aa aa vaja, ao 00000011, the Division into Groups scheme allocates memory modules 3, 15, 11, 7, dp of which this address is entered by the signal RAS1. After the address is entered through time ty (Fig. 12) is the signal + to bit e (j to

dq 0-2-00000100.20

which is signaled by the RAS2 signal to the remaining memory modules. After that, the signal B 0 changes to B about 1 and

  p, is 4 i3 tt 000000 The scheme of dividing modules into groups

selects modules 3, 12, 13, 14 for which this code is entered according to the signal CAS1. Then, after time t, the signal + to of comes (5L, which is CHANGE - 30

which goes to the address inputs of the memory modules:

Address Code

00000011 00000010 00000001 00000000

There are no states on the output of c - - 00000100, and this code is entered on the CAS2 signal into a stop; memory modules. Thus, the following address codes are stored in the memory modules:

Module number Address code

memory

30000001100000011

00000100000000 AND 0000001100000SUO

Address Code

00000 111 00000110 00000101 00000100

35

40

45

15, 11, 7

12, 13, 14

Oh, 1, 2, 4,

5, 6, 8, 9, 10 0000010000000100. The correspondence of these addresses to the required sample of a square is checked according to the table in FIG. 4,

Fetch address line

0000001 01 1 ooooooo; Go 1,

If, when sampling a square, there can be four different addresses in modules, then when sampling an arbitrarily located line, the address along the I axis is the same for all modules, and along the J axis it can be two addresses in bits eij "(and always different addresses in bits “(fiyt address change, in bits o (in (performed by dyadic method of connecting the address inputs of memory modules, and in bits ef | -f” (4 ea by dividing by

Module number

memory

Oh, 1, 2, 3

4, 5, 6, 7

8, 9, 10, 11

12, 13, 14, 15

The module-division group allocates the following modules; 9, 10, 11, 4, 5, 6, 7, О, 1, 2j 3, for which entry occurs by the signal RAS1. After this, the addition of +1 to the bit will occur - 25 do (4:

,, /, e /, oCg dg 4 fi 000001. which falls on the memory modules in the following form:

Module number

memory

Oh, 1, 2, 3

4, 5, 6, 7

8.9, 10, 11 12, 13, 14, 15

This code is entered into the memory modules with the numbers 12, 13, 14, 15, 8. After that, the BO becomes equal to 1, and S "00, In the result, a code is supplied to all the memory modules

about „- -o (00000010,

Finally, you can write:

Number 14 unit Address Code

memory

9,10, 11 4, 5, 6, 7 O, 1, 2, 3

12, 13, 14, 15,

80000001000000101

These addresses correspond to the highlighted -Q line.

Consider the division into groups with the same address. Unit 6 for dividing a group is for dividing memory modules into two groups, addresses that are on the J axis differ by + G, and into two groups whose addresses on the I axis differ by +1. At the output of the dividing circuit into groups we have N lines YR control unit 7 multi0000001000000001 0000001000000010 0000001000000011

five

0

0

which goes to the address inputs of the memory modules:

Address Code

00000011 00000010 00000001 00000000

Address Code

00000 111 00000110 00000101 00000100

five

0

five

Module number

memory

Oh, 1, 2, 3

4, 5, 6, 7

8, 9, 10, 11

12, 13, 14, 15

The module-division group allocates the following modules; 9, 10, 11, 4, 5, 6, 7, О, 1, 2j 3, for which entry occurs by the signal RAS1. After this, +1 will be added to the bit - 5 dy (4:

,, /, e /, oCg dg 4 fi 000001. which falls on the memory modules in the following form:

Module number

memory

Oh, 1, 2, 3

4, 5, 6, 7

8.9, 10, 11 12, 13, 14, 15

This code is entered into the memory modules with the numbers 12, 13, 14, 15, 8. After that, the BO becomes equal to 1, and S "00, In the result, a code is supplied to all the memory modules

about „- -o (00000010,

Finally, you can write:

Number 14 unit Address Code

memory

9,10, 11 4, 5, 6, 7 O, 1, 2, 3

12, 13, 14, 15,

80000001000000101

These addresses correspond to the highlighted Q line.

Consider the division into groups with the same address. Unit 6 for dividing a group is for dividing memory modules into two groups, addresses that are on the J axis differ by + G, and into two groups whose addresses on the I axis differ by +1. At the output of the dividing circuit into groups we have N lines YR control unit 7 multi0000001000000001 0000001000000010 0000001000000011

25. 149

ppexors and N control YC lines - a block of 8 multiplexers (FIG. 14). Those lines on which a logical unit signal is present allow the memory modules to receive a modified address from the RAS1 and CAS 1 signals, and those where zero, - on the RAS2 and CAS2 signals, the modified address, i.e., the address in which

25

In this example, the sampling square of the offset code along the axis J II and, therefore, units appear at the outputs 3, 7, 11,. The resulting code then passes through node 10 of the multiplexers, which is the upper half of the n-CUBE network at the i inputs. As a control code (control is magenta for compensating for 1: 1 dyadic shift in the placement of information), the code of displacement of a square is used along axis I (bit) Tsk as in each of the n network inputs

If the combinations are the same, and the upper ranks of the network rearrange groups of fl elements at once, then the input and output codes of the network in this mode coincide. Therefore, along the J axis there will be the following groups s: 3, 7, 11, 15 and 12, O, 4, 8,. 13, 1.5, 9, 14, 2, 6, 10, B modules

35

40

In this example, o (, lo the input code is as follows:

000 00 О О О О О 0--1 1 1 1, This code is fed to the input of the node 13 multiplexers, which is controlled as follows. Network breaks

five

26

The coordinates are no more than + 1. When the memory is working with square data blocks, the code converter 9 converts n / 2-bit input code (square offset code relative to the reference area, bit) into a code consisting of n identical groups in which the input code is converted to an inverse normalized unit code (Table 7), Table 10.

the memory with .numbers 3, 7, P, 15 is entered in the address (bits, corresponding to the J axis) by RA 51, and in the remaining ones - the modifier (increased by +1) by RAS2. For division into groups along axis I, a code converter 11, a multiplexer node 13 and a multiplexer node 12 are used. The code converter 1 1 converts the input p-bit code into an inverse normalized one. As an input code, I take the code of the square offset along the I axis (bits) which is used as the higher n / 2 bits of the input code, and the lower n / 2 bits are assumed to be zero. Thus, a code is obtained in which the number of zeros is equal to the number of, o, multiplied by the number n (Table 11).

Table 11

in n groups, as in the ordering of data, where each of the groups performs permutations among the network inputs, the numbers of which correspond to the numbers of memory modules in the square columns, and each group is controlled from 27

individually. An example of such a division for N 16 is shown, in FIG. 9 and 14. J Node 12 of ultiplexors switches control signals to al j (/ za (+1) // h in accordance with the magnitude of the square displacement along the axis J (), as shown in Table 12.

In this example, the displacement of the square along the axis J o / b (o, 11, (11 + 1) // 4 00. The matrix of control signals on the semi-network is as follows:

Go 01

OO

0O

1I GS NGO

0O

eleven

In accordance with this matrix, the input code is converted:

Number Input Output Code

49935528

the input p-bit code for shifting the initial element of the line relative to the field boundaries (bits cfjof o, of ,,) to the inverse normalized unit code. As an example, take you; 4, the line with the address 00000010110000000101. The offset code f 2 С, о 0101. The inverse normalized unit code is О О О О 1 1 1 1 1 1 1 1 11 1. The control code il. Therefore, after passing through the network, this code is converted

1111111101110000. In the memory modules numbered 9, 10, 11, 4, 5, 6, 7, O, 1, 2, 3, the address bits corresponding to the J coordinate are entered by the RAS1 signal, and in the remaining ones after modification by signal RAS2. In the row selection mode, the address modification in the bits corresponding to the I coordinate is not required, since this part of the address for

All 25 modules are the same. Therefore, the entry of the second half of the address in this mode can be performed on a single CAS 1 signal.

15

20

thirty

Claims (3)

1. A storage device with parallel random access to rows and data windows, containing a block of input data, a memory block, and 35 output data block, the information inputs of the device are connected respectively to the information inputs of the input data block, the outputs of which are connected respectively to the information inputs of the memory block, the outputs of which are connected respectively to the information inputs of the output data block, the outputs of which are connected respectively to the outputs of the device differing in that, in order to extend the functionality due to the additional format of calls in the form of lines, the address modification block is entered into it Block dividing into groups, the control unit, the first and second multiplexer units, wherein the first through ninth modification unit outputs connected respectively to the address LTD oh oh oh oh oh oh oh 1 1 1 1 about about about 1 oh oh oh oh oh oh 1 1 1 1 as a result, the address in modules 3, 12, 13, 14 is entered by the signal CAS1, and in the others - after modification by CAS 2. Consider the operation of the division scheme when fetching rows. When fetching rows, a 9 code converter converts thirty Invention Formula 0 1. A storage device with parallel random access to rows and data windows, containing a block of input data, a memory block, and 5 output data block, the information inputs of the device are connected respectively to the information inputs of the input data block, the outputs of which are connected respectively to the information inputs of the memory block, the outputs of which are connected respectively to the information inputs of the output data block, the outputs of which are connected respectively to the outputs of the device, different that, in order to extend the functionality due to the additional format of calls in the form of lines, an address modification block has been entered into it , the unit of division into groups, the control unit, the first and second blocks of multiplexers, while from the first to the ninth outputs of the address modification block are connected respectively to  the inputs from the first to the fifth block of dividing into groups, to the address inputs from the first to the third memory block and to the input of the river of the control unit, output 5 0 29 the first and second groups of which are connected respectively to the control inputs of the input data block and the output data block, the first and second outputs of the division into groups are connected respectively to the information inputs of the first and second multiplexer blocks, the outputs of which are connected respectively to the first and second recording inputs reads of the memory block, address inputs of the device are connected respectively to the inputs of the address modification block, inputs from the first to the fourth write-read devices are connected respectively to the first the control input of the first multiplexer unit, to the second control input of the first multiplexer unit, to the first control input of the second multiplexer unit, and to the second control input of the second multiplexer unit, 2, The device according to r. 1, about tl and - that the block division into groups contains the first and second code converters, the first, second and third nodes of the multiplexers, and the inputs from the first to fifth division blocks into groups are connected respectively to the inputs of the first and second code converters, to the control input of the first multiplexer node, to the control and output terminals of the second multiplexer node, the output of which is connected to the control input of the third multiplexer node, the outputs of the first and second converters. odov pod14 They are connected respectively to the information about the inputs of the first and the second summed inputs of the first and third nodes of the multiplexers, the outputs of which are connected respectively to the first and second outputs of the division into groups. 3. The device according to claim 1, wherein the control unit comprises first and second code converters, a group of modulo-two adders and a multiplexer node, the input of the mode of the control unit connected to the inputs of the first and second code converters and to the control input of the multiplexer node The outputs of the first group of which are connected respectively to the first information inputs of modulators modulo two groups, the outputs of the first code converter are connected corresponding to 10 15 9935530 To the second information inputs of modulo adders, two rpyi.m, i, the outputs of the second converter are connected to the information inputs of the multiplexer node, the outputs of modulo adders, two controllers, and the outputs of the second group of multiplexer nodes are connected respectively to the first and second groups of outputs of the control unit 4, The device according to claim 1, characterized in that the address modification block comprises first and second multiplexers, first and second modulo-two adders, the first and second registers, first to third adders, and the input of the address modification block is connected to n1m inputs of the first register, second register and the first information inputs of the adders from the first to the third, the outputs of the first adder, the first register, the second adder, the third adder and the second register are connected respectively to the first information inputs p The first and second multiplexers, to the second information input of the first multiplexer, to the second and third information inputs of the second multiplexer, the output of which is connected to the second information input of the first multiplexer, whose outputs from the first to the sixth are respectively connected to the outputs from the first to the sixth address modification block , the seventh and eighth outputs of the first multiplexer are connected respectively to the first 20 25 thirty 35 five 0 five modulo two, the outputs of which are connected respectively to the seventh and eighth outputs of the address modification block, the ninth output of the first multiplexer is connected to the ninth output of the address modification block, inputs from the first to fourth modes of which are connected respectively to the control inputs of the first and second multiplexers and To the second inputs, modulo two, the first and second adders, the first, second and third inputs of the address modification attribute of the address modification block are connected respectively to the second information inputs s first, second and third adders, carry output of the third adder connected to tpete.y data input of the second adder. eleven FIG. g one sixteen 13 75 17 Tsig.Z. 1499355 V gG, ITr TftVy Shch115 Shchtsd TlyVitV it fS rus o 9rus1 rusg YarusZ 1 / vfoW vft yiifitifs viyyudy at  , g TP-4 J-ft / f Vi with rso ToWOTWa a Tier1 oWoWoWob, viyody FIG. eight ygggg, ./tfe- ", -sxr in-y, g / -y yy, -Cr- / y, -" G7g- / .five inputs Wo viyody FIG. eight Inputs tppToWO OWO WOTSWBWo , I .ц,,, I ,, „,. Shdaoj onsussjesroniim Be FT lo WWCKW ol van e tkkz io W№4K: f 111  j y "tittle IB rZm m - - " ffi ti 3 Bbfxodbf FIG. 7 I Y5 531 w r-n5. I Ji i jdn f1 / g. 8 o and a ab ab about 1 3 about GT fT / SWnr 13 / "„ YarusZ Tier g rus rusz I rVV about 1 g 3 ti 5 B 1 8 9 Y 11 12 13 7tt 15 Tire lines / dff Hb / je FIG. Yu 149.9355 water Vshodlg fig.Z bus 0 f} Vj and Y, K, V, V, and V, o VnVnVaUftU "Lmmy /. Jj j i VHitr f f f g g rr L V tr, bttbi, v VgiftbJ-, v $ aiVyt i t i tftf GI / gi Address figg one FIG. 3 / / 0% / -. / -