SU1499264A1 - Digital phasemeter - Google Patents

Abstract

The invention relates to a radio metering technique and can be used to measure the phase angle between two signals. In order to increase accuracy and speed, one of the signals, between which the phase difference (reference) is measured, is converted to a square wave with a front coinciding with its zero transition. At the moment of the same null transition of another (investigated) signal, a short pulse is formed. In a special line, the square wave is filled with a series of quantizing pulses that are out of phase and rigidly synchronous in time with the front of the square wave. The number of pulses from the output, in which the phase shift relative to the zero transition is zero, is counted before the arrival of the pulse from the zero transition of the signal under study and is an integer number of "quanta" of the phase. The signals from the outputs of the chain of delay elements form a code that varies over time so that each fraction of the current (unfinished) "quantum" phase is marked. At the moment when the pulse from the zero transition of the signal under study arrives, said code is written into the second register, and at the same time the contents of the counter of whole quanta of the phase present at that moment are copied to the first register. The sum of the numbers recorded in the first and second registers, taking into account their weight, determines the desired phase difference. The synchronism of the quantizing pulses and the possibility of determining the fraction of the "quantum" of the phase ensure the achievement of a positive effect. 5 il.

Description

The invention relates to radio measuring equipment and can be used to measure the phase angle between two periodic electrical signals.

The purpose of the invention is to increase the accuracy and speed of the device.

1 shows a block diagram of the device; 2 shows time diagrams of a, b, c, d, d, g, and signals at the corresponding characteristic points of the circuit; FIG. 3 is a schematic illustration of the process of marking, quoting, and encoding the shares of the current, quantum and phase relationships of the signals at the outputs of a quantizing delay line (also by charts of logical signal levels); Fig. 4 shows time diagrams a, b, c, f, c, d, l, 3, and signals at the corresponding points of the circuit when the second input signal appears ahead of the first one and the corresponding change of the phase sign; on kg.5 - funk31499264

national scheme for the implementation of the adder-decoder.

The digital phase meter contains a shaper 1 of the reference half-period, a shaper of 2 pulses of the signal under study, and the platoons of the formers 1 and 2 are connected to the corresponding outputs of the switch-3 input signals. The first direct output of the driver 1 of the reference half-period and the output of the driver 2 pulses of the signal under investigation are respectively connected to the inputs of the key element 4, the output of which is connected to the input 15 of the trigger 5 of the character extraction, the output of the latter is connected to the control input of the switch 3 and to the sign information output of the phase meter. . The second (inverse) output formate 20 l 1 of the reference half period is connected. ; with the input shaper 6 pulses; an inverted reference signal and, through a delay element 7, with an input of the imager 8 of the zero-resolution enable pulse 25, the output of which is connected to the control input of the counter 9 quantizing pulses and to one of the control trigger 10, the output of the latter is connected to one of the .30 inputs of the second the key element 11i The phase meter also contains the first register 12, the second delay element 13, adder-decoder 14, in the second register clock 15 and the quantizing line 16, delay, consisting of the elements OR 17.1, .., 17 .P with direct and inverse outputs (OR-NOT / AND AND) between the first; the output of each of which and the first input of the subsequent one includes the elements .40 you 18.1, .. ,, 8, n-1 of the delay, as well as an additional element 19 of the delay {connected between the second input of the first; element OR-NOT / OR 17.1 and BTO-V eye output of one of the other elements of the W-NOT / OR 45 quantizing delay line. The first input of the first element is STA-NOT / OR 17.1 and the second inputs of All the rest of these elements are the -LINE input of line 16, which is CONNECTED-JQ

vat to the nepBO fy output of the driver 1 support half period. The second outputs. All elements 17 of line 16 are connected to the I inputs of the second register 15, the first input of which is connected to the “counting input of the counter 9 quantizing pulses, the information outputs of which through the first register 12, used to record an integer number of periods of quantizing pulses, are connected To the information inputs of the adder-decoder 14, to the second information inputs of which the information outputs of the second register 15 are connected, the information outputs of the adder of the decoder 14 are the output of the device. The output of the driver 2 pulses of the signal under study is connected to the control inputs of the first and second registers 12 and 15, the output of the key element 4 through; The second delay element 13 is connected to the second input of the control trigger 10, the output of the inverter 6 pulse generator 6 is connected to the second input of the second key element I1, the output of which is connected to the control input of the decoder 14,

The second register 15 contains the same number of bits as the number of phases generated in a quantum line: 16 delays (Fig. 1 and 3 show the generation of standard-phase signals). The recording of signals into the register should be carried out in a time shorter than Tsb / 2n where n is the number of countable fractions of the period of quantizing pulses, Tce is the period of quantizing pulses. The duration and shape of the control signals are determined by the formers 2 and 6,: The adder-decoder 14 (FIG. 1) summarizes the information from the registers 12 and 15 with an appropriate weight, ensuring at the same time writing the received code to the output register by an external command . An example of the implementation of the adder-decoder is shown in Fig. 5. The code corresponding to the number of past total quanta comes from register 12 to multiplier 20, where it is multiplied by a constant value / equal to 2n (the number of countable fractions of the period of alternating pulses). The resulting number is summed in adder 21 with the number of counted up-; Leu in the last part of the incomplete quantum, which comes from register 15, and transmitted to the decoder 22. In the decoder, the code corresponding to the total number of quanta counted is converted into a phase difference code. The result is written to the output register 23 by a command from the key element 11,; The pulse shaper of the studied signal is provided by the dividing device 51499264

the pulse width is less than the duration of the counting fraction of a quantum (i.e., / 2n). The peak of the pulse can be

1 and logs10

15

20

thirty

as logical 1, depending on the chosen implementation of the key element 4 and registers 12 and 15 (figure 1). In the time diagrams (Figures 2 and 4), it is assumed for definiteness that the vertex of the pulse corresponds to a logical zero.

Key element 4 (fig.1) must pass a pulse from generator 2 only if the signal at the output of generator 1 of the reference half-period corresponding to the locked line 16. In the time diagram of FIG. 4, this state corresponds to logical 1 at point b. .

Counter 9 of quantizing pulses counts through transitions from a logical zero to a logical one, and depending on the signal at the control inputs, either 25 pulses are counted or the code applied to its information inputs is recorded.

The device works as follows.

In the initial state, i.e. in the absence of signals U (and Ua at the inputs of the switch 3, at the output L (Fig.5, 2, 4) of the former 1, the level of the logical unit (high level) takes place, respectively, at the direct outputs of the elements OR NOT / OR 17.1-17 .P will also have levels of logical units, and at their inverse levels logical levels of zero.The state of switch 3 depends on the state of the sign allocation trigger 5. In this case, two variants of state are possible: the first, when the output of the trigger 5 has the potential potential of logical 1, and the voltage 11 goes to the generator 1 through you one in point O as a reference voltage, and U to driver 2 through an output at point: $ as the voltage to be tested; second, when the output of trigger 5 has a logical O potential, and voltage U goes to driver 2 in As a study, the voltage, and the voltage UQ. - .former 14 as the reference one, I Device operation is described in two possible cases. In the first case, the switch 3 is turned on by option 1; strain stress35

40

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phase out from T ;, less than 180 ° (in all explanations, the steady state mode is meant). With appearance

The signal Itz and ll / j at output b is set to a square wave with the frequency of the reference signal. The negative front and further low level of the meander fypoBeHb logical zero) from the output of block 1 forms a low 11 level at the direct output of the OR-NOT / OR 17.1 element and allows the formation of low levels at the direct outputs of the 17.2-17 elements. () Line 16. Low level from the first exit of an element 17.1 with Z aU t

Tk

  on the item

P

18.1

0

0

five

five

0

five

five

delays (where Tkv is the period of quantizing pulses, n is the number of forming elements 17) enters the input of element 17.2 and forms a low level at its direct output and a high (logical 1) at the inverse output 24.1. Further, the low level passes along the line from the elements 18.2-17.3-18.3-17.4 ...- 18.p-1-17.P with a delay in each group of elements 18-17 by the same value ut, and the high level passes with a delay t (j in element 19 to the second input of element 17.1 and locks it, forming a high level at its direct output again. Amount of delays

Tkb

must be equal

Privately, ut, +

0

tea, shown in figure 1,

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It should be noted that the delay element 19 can be connected to the inverse output of any other element 17. It suffices only to satisfy the conditions

Ut5. + mAt, m is the element number OR-NOT / OR 17, the output of which is connected to the additional element / 19 delay,

n m -.

The high level formed spreads along the chain 17-18-17 with the same delays as the low one. As a result of successive shifts of low and high levels, the inverted outputs 24.1-24.p are set to the signals, the time diagram of which is shown in FIG. 3 for

case n 5, m 1. Their period is equal to the period of the quantizing signal. These signals exist as long as the output of the L driver 1 is maintained at a logic zero level (low level), i.e. in the first half period of the operating frequency.

From the output 24.1, the quantizing signal arrives at the counting input of the counter 9, which increases the content along the transitions from the logical O to the logical 1, i.e. on positive fronts. Since the first positive front is by 14992648

 (Fig. 3, which shows the signals in the form of logical levels, and the codes are recorded in the table in the table at the bottom of the figure for the case I n 5). Consequently, the code value in the interval between the counted edges of the quantizing pulses determines the fraction of the current quantizing period that passes by the time of reference to the resolution Tz, / 2n.

At the time ti2i (figure 2), corresponding to the negative zero crossing of the investigated signal of the MCSS

is simultaneously with the front of the foot-; 15 at the output of the imaging unit 2 forms;

with a short pulse (figure 1 and 2, the diagram at the point F). This impulse gives a command to registers 12 and 15 on: recording information. Register 12 is for-: an integer number of quanta is written that passed before the instruction to write information was received, and register 15 is assigned a code corresponding to the fraction of the uncommitted quantum (according to signals 24.1-24.P).

the half period, the number of pulses counted by counter 9, per unit, exceeds the number of passed whole phase quanta. To eliminate this effect, as well as to eliminate the effects of possible interference, the counter 9 is zeroed in front of; each counting cycle. In order to ensure this, the negative front of the inverted reference half-period from driver 1, corresponding to the moment when the quantizing pulses are generated, is delayed in element 7 for a time interval just smaller than the reference half-period, and fed to the driver 8, in which a pulse is created with a front coinciding with the front come; meander, and such a duration, / so that its cut (time t in figure 2) was ahead of the positive front of the reference half period at the inverse output of driver 1 less than the quantum period, (figure 2, the signal at point c |). This pulse is applied to the control inputs of counter 9 and enables the recording of signals from the information inputs of the counter on which the logic zero levels are permanently set. Since the resolution comes before the first positive Lront, this front has zeroed the counter, and the counting starts from the second front. Consequently, the exact number of passed whole quanta is counted in the counter. Intervals smaller than a quantum are monitored by signals from outputs 24.1-24.p. The distribution of these signals over time is depicted in FIG. If you simultaneously record signals; from all outputs 24.1-24.n at the same time, they form an n-bit code that varies in time with step

0

five

0

with a short pulse (figure 1 and 2, the diagram at the point F). This impulse gives a command to registers 12 and 15 on: recording information. Register 12 for-: i writes an integer number of quanta that passed before the instruction to record information arrived, and register 15 to write the code corresponding to the fraction of the uncommitted quantum (according to signals 24.1-24.P).

; Information from both registers is supplied to the adder-decoder 14.; In it, the number of integer periods is summed with the fraction of the last incomplete quantum, converted into a phase difference code, and stored.

Permission to memorize (update) information at the output of the totalizer-decoder 14 comes from the output Z of the imaging unit 1 through the imaging unit 6. The imaging unit 6 generates -im-, pulse at the time (Lig.2) of the negative transition through the zero signal at the output 2 . Due to the forward output of driver 1, this will be a pulse at the moment of zero crossing of the reference signal in the positive direction. This pulse passes through the prepared key 11 and gives the command to the adder-decoder 14 to memorize information.

The preparation of the second key element 1I is carried out by trigger 10, which, by a pulse from the output g of the driver 8, is set to the logical 1 state.

Time diagrams of the processes in the phase meter shown in Fig.2.

In the second case, the switch 3 is switched on according to option 1, but the voltage Uij is ahead of U4 in phase by no more than 180 (figure 4). Then the blocks 1,17i 18,19,8 and 9 work as well as in

0

five

ten

15

91499264

case 1, but the impulse from the driver 2 command to fix the difference value φ | az) comes when the level of the logical zero of the reference half-period at the output E of the driver 1: has already been replaced by the level of the logical unit. This level arrives at key element 4, prepares it for operation, and when a pulse appears at the output of shaper 2, it passes through element 4 to the input of trigger 5. The output signal of trigger 5 changes from 1 to O, and the switch 3 switches according to option 2. In this case, the zero logic signal from the output of flip-flop 5 will be perceived at the information output as a plus sign (the signal under study is ahead of the reference one),

When switching switch 3, logic level 1 at output B of driver I changes to logical O. Due to the inertia of switch 3 and controls, this change may be delayed and thus introduce an error into the next aa measurement cycle. In order to eliminate this phenomenon, an additional signal from element 4 through the second delay element 13 (with a delay slightly shorter than the half of the square wave period) places the trigger 10 in the logical zero state, i.e., locks the second key element 11. Thus, the command to pass on for- (c) the information at the output of the adder-decoder 14 to the next 20

25

thirty

35

normal (without switching 40) measuring cycle.

From the description of the operation of the phase meter, it can be seen that both when the first signal is ahead of the second signal and when it is left to stand, the device 45 will have information about the magnitude and sign of the phase difference.

The positive effect of the proposed device is that simultaneously increases the accuracy of determining the phase difference of the phase difference and provides a measurement of the phase shift in one period of the reference signal, which improves performance. At the same time, all other things being equal, an increase in the accuracy is not associated with a decrease in speed.

The use of a coherent quantized signal completely

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ten

0

five

0

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0

There is additional error due to. nonsynchrony of the quantizing signal and the time interval filled by it corresponding to the phase shift angle. The interval between the moment of arrival of the command to the measurement and the cut of the last quantizing signal is controlled by fixing the code from the outputs of the scientific research institutes. Therefore, the error also decreases due to the non-multiplicity of the quantum period to the length of the measured interval.

Claims (1)

Invention Formula A digital phase meter containing a shaper of the reference half-period and a shaper of the pulses under study, the inputs of which are connected to the corresponding outputs of the switch of input signals, the first output of the shaper of the reference half-period and the output of the pulse shaper of the signal under investigation are respectively connected to the inputs of the key element whose output is connected to the trigger trigger input the sign, the output of the latter is connected to the UPP by the equal input of the switch of input signals and is significant; information output, the second output of the shaper of the reference half-period is connected to the input of the shaper im5 0 five g pulses of the inverted reference signal, a zero-resolution enable pulse driver, an output connected to the first input of a control trigger, the output of which is connected to the first input of the second key element, the first and second registers, the first and second delay elements, and a quantizing pulse counter, characterized in that in order to increase accuracy and speed rotsii, additionally entered the adder-decoder, quantizing delay line, consisting of n + 1 OR elements, between the first output of each of which and the first input of the subsequent inclusion n quantizing delay elements, and additional delay element, I included between the second input of the first element OR and the output of one of the subsequent elements OR a quantum-. delay line, the first input of the first element OR, and the second inputs of all the other elements OR eleven The second outputs of the OR elements are connected to the inputs of the second register, the first input of which is connected to the counting input of the quantizing impulse counter, the control input of which is connected to the first input of the control trigger and whose information outputs through the first the register is connected to the first information1) 1m inputs of the adder-decoder, the second information inputs of which are connected to the information outputs of the second register, the second output of the reference half The period is connected via tiy Shee pulses  tjaijf hvnnzh} four 12 first delay element With the input of the resolution enable pulse generator, the output of the pulse generator of the signal under study is connected to the control inputs of the first and second registers, the output of the first key element through the second delay element is connected to the second input of the control trigger, the output pulse generator of the inverted reference signal is connected. to the second input of the second key element, the output of which is connected to the control input of the adder-decoder, whose information outputs are inputs digital phase meter. Puz.1 uZfi  And FSh.1 w ill Я5 KoSbt BUT outlet line F 93MfWa, / w9aaaa W r "j V Phi1.5 fyuZ