SU1498902A1 - Device for controlling combination lock - Google Patents

Abstract

The invention relates to devices for protecting various objects from unauthorized access and improves the secrecy of the device. The KS 1 codes are stored in memory blocks 6.9, the KS 2 codes are stored in memory blocks 7, 10, and the QC code in block 8. In the coupled state, the modulo two codes of the CC 1 and a random sequence, which is fed through the connector 11 to the input "8" (eight weights) of the decoder 13, are successively output from the counterpart to the key. From blocks 9,10,8 memories are read codes that arrive respectively at the inputs "1", "2", "4" of the decoder 13, the input "16" of which receives the contents of the delay block 16. The signals from the output of the decoder 13 are received respectively through the element OR 15 to the input of the delay block 16, and through the element OR 14 and connector 11 to the input of the element Exclusive OR 3. The input of the element 3 receives the arithmetic sum of the code of COP 2 and a random sequence. In case of equality of the KS 1, KS 2 key codes and the counterpart from the output of the Exclusive OR 3 element, a QC code is output to the output block 12. 1 tab., 1 Il.

Description

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The invention relates to a technique of storage (ity of various objects from access by unauthorized persons, in particular to electronic code locks.

The aim of the invention is to increase secrecy.

The drawing shows a functional diagram of the device.

The device contains a synchronization block 1, a generator of 2 random numbers, elements of the source and 3 or 4j block 5 add 3 block 6 of the lock code memory, blocks 7 and 8 of the key code memory, blocks 9 and 10 of the corresponding code memory, electric connector 11, output unit 12J decoder 13, elements OR 14 and 15, and block 16 delay.

The device works as follows.

When the key is docked with the counterpart, the limit switch (not shown) of the synchronization unit 1 is triggered and the latter begins to generate clock pulses T1 and T2 with a certain delay. The clock pulses T1 arrive at the inputs of blocks 6 and 7 of the memory, the generator of 2 random numbers, block 5 addition and through the connector 11 to the inputs of blocks 8–10 of memory of block 16 of delay. The clock pulses TZ are fed to the input of the output unit 12.

In the first clock cycle T1, the first bit of the code of correspondence KC1 is read out from memory block 7 and the modulo two is added to the element RETAILED OR 4 with the first bit of a random sequence of generated

torus 2, and is outputted via connector 11 to input c. weighing 8 decoder 13. The same bits from blocks 8-10 of memory receive the first bits of the corresponding KC1f KS2 codes and key code, which are fed to inputs 1, 2, 4 of the decoder 13. In addition, the contents of block 16 are read by tact T1 delays that arrive at the input 16 of the decoder 13, Depending on the value of the codes presented in the table, and the inputs to the inputs of the decoder 13, one of the outputs of the latter generates a logical 1 signal, or logical O are set at all outputs of the decoder 13. at the outputs of the elements OR 14 and 15 signals are generated according to

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truth table. The signal from the output of the OR 15 element is fed to the input of the delay block 16, which is stored on the trailing edge of the T1 clock until the next T1 pulse arrives. The signal from the output of the element OR 14 is fed through the connector 11 to the input of the element EXCLUSIVE OR 3. At the same time, the first digit of the code of the corresponding B1; The CC2 is read from memory block 6 and is summed at block 5 with the first digit of the random sequence. Coming from the output of the generator 2. The result of the addition from the output of block 5 is fed to the EXCLUSIVE OR 3. If the codes for correspondence KC1 stored in blocks 7 and 9 of memory are identical, and the codes for correspondence of KC2 are stored, they are stored in blocks 6 and 10 of the memory, at the output of the EXCLUSIVE OR 3 element, the first bit of the QC key code is allocated, which is fed to the input of the output block 1 2 and is recorded by the pulse T2

into it. A similar process takes place on the second cycle T1 and T2, etc.

If the correspondence codes of the key and the counterpart do not match, which happens when the key is used, the key code entering output block 12 is distorted, and therefore there is no access to the protected object.

After receiving the key code completely into the output block, the key exchange process with the counterpart is stopped and from block 1 of synchronization to block 12 a signal TZ is received allowing the issuance of the key code to the protected object.

After the key is disconnected from the response part, the permission signal from the output of the synchronization unit 1 is removed and the key code to the protected object is terminated;

Unlike the known devices, where the operations on identification codes in the key are carried out sequentially) and as a result of malfunctions), namely, the connection between the output of the key addition unit and the input of the element BATTING OR, or short circuit at the output of the addition unit, or a short circuit at the input of an EXCLUSIVE OR element connected to the output of the addition unit, or as a result of faults in the addition unit

and the element EXCLUSIVE OR, which leads to similar consequences, results in the issuing of the QC key code (or its inversion) when the key of any code is input to the key. Moreover, this situation may arise with probability P, a much greater probability of selecting a code P. For example,

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ten

then P, Pj.

In the proposed device, in the key, operations on identification codes are performed in parallel. We show that single element failures do not lead to the issuance of a key code explicitly. When the device is working properly, the sequence formed at the input of the key is described by the equation F ((T ® KS1) + KC2) ® KK, where T is the sequence coming from the counterpart,

In the worst case, single faults can lead to the omission of the code KS1 or KS2, i.e. when the code KS1 and KS2 is equal to the constant O or 1. This can occur in case of failure of memory blocks 9 and 10 or malfunctions in the input circuits of the decoder 13 (for example, in the event of breaks or short circuits of its inputs connected to the outputs of blocks 9 and 10 memory). In other cases, single element failures (decoder 13) lead to the formation of a false value F, on certain sets of input variables and do not lead to a key code explicitly,

Consider the options that arise when considering the worst case.

At the output of memory block 9, a zero code is constantly generated. In this case, the function is determined by

Therefore, in the best case, the issuance of a key code can occur with 15 occurrences of binary faults. In the 3TCW case, the probability of malfunctions per day is determined by the expression

20

P, (1-T) H

Polaga, we get P- 5.8-10-.

The obtained value is less than the considered value Р „3,

Thus, the proposed device has a higher secrecy than the known.

Claims (1)

30 Formula of the invention: Eni Code lock control device containing synchronization unit, random number generator, elements 35 EXCLUSIVE OR, addition unit, lock code memory block, key code memory blocks, match code memory blocks, electrical connector, the first output of the synchronization block connected to the random number generator input, lock code memory block input, the input of the first block of the key code memory, the first input of the block. marriages and through the first couple of contacts 45 electrical connectors with inputs of the first block of memory of the correspondence code, of the second block of memory of the corresponding code, of the second block of memory of the code Fj (T + KC2) © KK, i.e. The key code is not explicitly issued from the key. key, the output of the random 5Q number generator is connected to the second input of the Adding unit and the first input of the second element EXCLUSIVE OR, the second input of which is connected to the output of the first memory block of the key code, code code At the output of memory block 9, a permanently 55 lock code memory is connected to the third, a single code F (T ®) is formed by the input of the addition block, the output of the KC2 ® KK (T + KS2) (J) KK block, i.e. The addition code is connected to the first input with the key code explicitly from the key of the non first element EXCLUSIVE OR, which is distinguished by the fact that. At the output of memory block 10, a zero code F ((T (5 КС1) + 0) ® КК Т ® КС1 (5 (+) КК) is constantly formed. At the output of memory block 5, a single code Fg ((T® КС1) + 1) ® КК Т © КС1 + + КК is constantly formed. Thus, the occurrence of single faults does not lead to the issuance of the QC key code explicitly. Therefore, in the best case, the issuance of a key code can occur when binary faults occur. In the 3TCW case, the probability of malfunctions per day is determined by the expression 20 P, (1-T) H Polaga, we get P- 5.8-10-. The obtained value is less than the considered value Р „3, Thus, the proposed device has a higher secrecy than the known. Formula of the invention: Eni Code lock control device containing synchronization unit, random number generator, elements EXCLUSIVE OR, addition unit, lock code memory block, key code memory blocks, match code memory blocks, electrical connector, the first output of the synchronization block connected to the input of a random number generator, the input of the lock code memory block, the first input the key code memory block, the first input of the memory block and the first pair of contacts electrical connector with inputs of the first block of memory of the correspondence code, of the second block of memory of the corresponding code, of the second block of memory of the code in order to increase secrecy, it contains an output block, a decoder, OR elements, a delay block, the second output of the synchronization block is connected to the first input of the output block, to the second input of which the EXCLUSIVE OR element is connected, the output of the first code memory block i is connected to the input of the decoder with a binary weight of 1, the output of the second memory block of the code is co.t. — the branch is connected to the input of the decoder with a binary weight of 2, the output of the second memory block of the key code is connected to the input of the decoder of binary weight 4, to in A Binary weighing 8 is connected to the output of the delay unit — its first input is additionally connected via the first pair of electrical connector contacts to the first output of the synchronization block the decoder input with a binary weight of 16 is connected to the output of the second element EXCLUSIVE OR via the second pair of connector terminals, the decoder outputs the tenth weights of 1, 2, 4, 8, 16, 19, 21, and 25 are connected respectively to the first, second, third, fifth, ninth, tenth eleventh and thirteenth inputs of the first OR element, the decoder outputs with the decimal weights of 3, 9, 10, 15, 18, 24, 27 and 30 are connected respectively to the first, third, fourth, eighth, ninth, eleventh, thirteen and M fifteenth inputs of the second element of the ILIZ outputs a decoder with decimal scales 7, 11, 13, 14, 22, 2b, 28 and 31 are connected respectively to the fourth input of the first OR element and the second input of the second OR element to the sixth input of the first OR element and the fifth input of the second OR element, to the seventh input of the first OR element and the sixth entrance of the second element OR, with the eighth entrance of the first and the seventh entrance of the second OR, with the twelfth entrance of the first and tenth input of the second element OR, with the fourteenth input of the first and twelfth entrance of the second element OR, with the fifteenth entrance of the first and fourteenth input of the second element OR, with the sixteenth entrance of the first and sixteenth entrance of the second element OR, output the first element OR is connected to the input of the first element EXCLUSIVE 1, OR, through the third pair of electrical connector contacts, the output of the second element OR is connected to the second input of the delay block. 1498902 10 Continuation of the table