SU1495985A2 - Device for control of alternation of pulse signals - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing to control pulse sequences. The device for controlling the sequence of alternating pulse signals contains input buses 1, switch 2, element EXCLUSIVE OR 3, element OR 4, counter 5 pulses, output bus 6, elements 7 and 9, HE 8. Detection of simultaneous arrival of pulses on input buses increases reliability of control 1 il.

Description

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The invention relates to a pulse technique, can be used in automation and computing to control pulse sequences, and is an improvement of the invention according to the author. No. 1256184.

The purpose of the invention is to increase the reliability of control due to the detection of simultaneous arrival of pulses on the input tires. I The drawing shows the structural scheme of the device. I The device contains input buses 1, 5: which are connected bitwise to the information inputs of switch 2 and, {the inputs of the elements EXCLUSIVE OR 3 | AND I 4. The output of switch 2 is connected to the counting input of the counter 5 pulses. The output bus 6 is connected 1C by the output of the first element I 7; the first- | which input is connected to the output; the element OR 4, and the second entrance - with you14959854

FINAL OR 3, an analysis is performed of the simultaneous arrival of several signals on the input buses 1 of the device. If the signal is present only on one of the inputs of the EXCLUSIVE OR 3 element, then a single level signal is present at its output, if the signals are more than 20

5Q more than at one input, then at the output of the element is EXCLUSIVE OR 3 signal of zero level.

Element OR 4 implements the analysis of the presence of pulses at the input buses of the ax 1 device, i.e. if there is a signal at least at one of the inputs of the element OR 4, at its output there is a signal of a single level. Thus, with the correct alternation of signals at the input busbars of the 1 device, at the outputs of switch 2, elements 3 and 4 there are single level signals.

If there is a NE 8 switch at the outputs with an input 8. The input of which I is connected to the output of the second element | AND 9, the first and second inputs of which are connected to the outputs of the I switch 2 and the EXIDENT ID 3 element. The outputs of counter 5 are alternately connected to the address inputs switch 2.

The device works as follows.

Before starting work, the 5 US-Devices counter proceeds as follows. For example, after the signal arrives at the first of the output buses 1, the signal arrives at the third of the input buses 1. At the output of the switch 2 in this case there is a zero level, since the code on the address inputs of the switch 2 connects the second of the input buses 1 to its output PPI 4 and EXCLUSIVE OR 3 elements are single level signals. Thus, the signal of the zero level arrives at the first input of the AND 9 element, and the signals of the single level arrive at the second input of the AND 9 element and the first input of the And 7 element. On bus 6, a single level signal indicates a faulty situation.

It is turned into a zero state by any known method (reset circuits are not shown). The outputs of counter 5, which are connected to the address inputs of switch 2, specify the number of the input bus 1 polled. When the counter 5 is set to zero, the output of switch 2 connects the first of the device input buses 1. . The signal received at the first input of switch 2 passes to its output and the counting input of counter 5.

At the end of the input signal, the counter 5 changes its state to the next one, thereby connecting the next one to the output of the switch 2, i.e. the second of the input rails 1. If the input signals are interleaved correctly, the process is repeated. Each of the signals arriving at the output bus 1 of the device also arrives at the corresponding input of the EXCLUSIVE OR 3 and OR 4 elements. On the EX element

more than one input, the output of the element is EXCLUSIVE OR 3 signal of zero level.

Element OR 4 implements the analysis of the presence of pulses at the input buses of the ax 1 device, i.e. if there is a signal at least at one of the inputs of the element OR 4, at its output there is a signal of a single level. Thus, with the correct alternation of signals at the input busbars of the 1 device, at the outputs of switch 2, elements 3 and 4 there are single level signals.

If there are elements 3 and 4 of signals of different levels on the outputs of switch 2, bus 6 contains a single signal indicating a faulty situation, and if all three signals are of the same level

(indifferently single or zero) on bus 6 is a zero signal.

In case of violation of the order of alternation of signals on the input buses 1 work

The devices proceeds as follows

zom. For example, after the signal arrives at the first of the output buses 1, the signal arrives at the third of the input buses 1. At the output of the switch 2, in this case there is a zero level, since the code on the address inputs of the switch 2 connects the second of the input buses 1 to its output. The outputs of the PPI 4 and EXCLUSIVE OR 3 elements contain single level signals. Thus, the signal of the zero level arrives at the first input of the AND 9 element, and the signals of the single level arrive at the second input of the AND 9 element and the first input of the And 7 element. On bus 6, a single level signal indicates a faulty situation.

In the case of simultaneous arrival of two or more signals to the input buses 1 of the device, one of which comes from the bus defined by counter 5, a single level signal is present at the output of switch 2.

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At the output of the element, the EXCLUSIVE OR 3 signal is zero, since at the inputs of element 3 there are simultaneously several signals,. At the output of the element OR 4 there is a signal of a single level. Thus, at the first input of the element And 9 the signal of a single level is fed to the second input of the element And 9 - a signal of the zero level, and at the first input of the element And 7 - a signal of a single level. On bus 6, a single level signal is generated, signaling a faulty situation.

In the case of simultaneous receipt of two or more signals to the input bus 1 of the device, and none of which goes to the bus defined by counter 5, the output of the commutator 2 has a zero level signal, the output of the element is EXCLUSIVE OR 3 - a signal of zero level, and at the output of the element OR 4 - a signal of a single level. On buses 6 there is a signal of a single level, which is a sign of a faulty situation.

At the times when there are no signals on the bus 1 of the device, the output of the switch 2 is present

the signal is zero, the output of the element is EXCLUSIVE OR 3 is the signal of zero level, at the output of the element OR 4 is the signal of zero level. Therefore, on bus 6 there is a zero signal.

Thus, the proposed device monitors the alternation of asynchronous signals and generates a failure signal both in case of a violation of the order of signals on the input buses, and when several signals are received instead of one

Claims (1)

Invention Formula A device for controlling the sequence of the alternation of pulsed signals by aut. St. No. 1256184, characterized in that, in order to increase the reliability of monitoring by detecting simultaneous arrival of pulses on the input buses, a second AND element is inserted into it, connected between the switch output and the input of the element NOT, as well as the element TRUCKER OR, whose inputs are jumbled with the input tires, and the output - with the second input of the second horn of the element I.