SU1493991A1 - Dc voltage stabilizer with overvoltage protection - Google Patents

Abstract

The invention relates to electrical engineering and can be used in thyristor compensators of reactive power, electric drives of direct and alternating current as a power source for control, regulation and protection devices. The goal is to increase accuracy and noise immunity while simplifying overvoltage protection configuration. The goal is achieved by the fact that in the current overload mode, the current sensor 14 through the trigger-blocking node 20 locks the regulating element 1 with a "latch", limiting the load current to zero. When the output voltage rises above the nominal value, the feedback node 2 generates at the output the error signal locking the regulating element 1. 1 sludge.

Description

The invention relates to electrical engineering and can be used in thyristor compensators of reactive power, electric drives of direct and alternating current as a power source for control, regulation and protection devices.

The goal is to increase accuracy and noise immunity while simplifying overvoltage protection configuration.

The drawing shows a stabilizer with overvoltage protection.

The stabilizer contains a regulating element 1 made on an integral transistor, the base of which is the control input of the regulating element: a feedback node 2 consisting of an output voltage divider 3 made on a potentiometer connected to the output pins of the stabilizer, the average output of which is output divider output voltage from the source of the reference voltage 4, made in the form of a circuit connected in series resistor 5 and zener diode 6, connected to the output pins of the stabilizer, from operational amplifier 7, the output of which is the output of the feedback node, from oppositely connected diodes 8 and 9 connected between the inverting and non-inverting inputs of the operational amplifier 7, to the first input resistor 10 connected

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the inverting input of the operational amplifier 7 and the output of the output voltage divider 3, the second input resistor 11 connected between the non-inverting input of the operational amplifier 7 and the connection point, the resistor 5 and the zener diode 6 of the reference voltage source 4, made in the form of a circuit connected in series JQ a ballast resistor 12 and a stabilizer 13, an anode connected to a common power bus, the operational amplifier 7 connected to the common spruce bus and to the connection point of the zener diode 13 and a ballast resistor 12 connected to the output of the feedback node 2; load current sensor 14, consisting of current shunt 15, resistor 20 16, potentiometer 17, first transistor 18, the emitter of which is connected to the first output of current shunt 15, the base is connected to the middle output of potentiometer 17 and the collector 25 is connected through resistor 16 through the common power and the second transistor 18, in which the emitter is connected via potentiometer 17 to the second output current shunt 15, the collector ZO is connected to the common power bus and the base is the input for the load current sensor 14, the output of which is The collector of the first transistor 18 and the resistor 16; trigger-blocking node 20, consisting of a shunt transistor 21, in which the emitter is connected to a common power bus, and the collector is the output of blocking the trigger-blocking node 20, the first 22, second 23, third 24 and fourth 25 resistors, from the first 26 and second 27 diodes, the light-emitting diode 28 and the photothyristor 29, in which the anode is the power input of the trigger-blocking node

20, and the cathode is the output of the state of the three-blocking node

20 and connected via a third resistor 24 to the base of the shunt transistor

21, and through a quarter resistor 25 with a common power, the first input of the trigger-blocking node 20 is connected via the first resistor

22, the first diode 26 and parallel to the co-55 diode light-emitting diode 28 and the second resistor 23 with a common power bus, and the second input of the trigger block

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kirovochnogo node is connected through the second diode 27 and the second resistor also with a common power bus node delay 30, made in the form of an inertial KS-link on the resistor 31 and the capacitor 32; logic element 33, consisting of the first 34, second 35 and third bc diodes, first 37, second 38 and third 39 resistors and from transistor 40, at which the collector is connected to the power supply terminal of the And element and through the first resistor 37 with anodes the first 34, second 35 and third 36 diodes, and the emitter is the output of AND 33 and is connected through a third resistor to a common power bus, and the cathodes of the first 34 and second 35 diodes are the first and second inputs of the logical AND element, respectively; 36 diodes connected to the base t anisistor 40 and through the second 38 resistor with a common force, the first parallel shunt element 41 connected between the output pins of the stabilizer and consisting of a series-connected current limiting resistor 42 and a thyristor 43, the control output of which is connected via a resistor 44 to the control input of the first a parallel shunt element 41; a second parallel shunt element 45, consisting of a current limiting resistor 46 and a transistor 47, in which the base is connected via a resistor 48 to a control input of a second parallel shunt element 45; the emitter is connected to the positive output terminal of the stabilizer, the collector is connected via a resistor 46 to the common power bus, and the collector junction point of the transistor 47 and the resistor 46 is the output of the state of the second parallel shunt element; the tripping element 49, made in the form of a flat insert, with the common power bus connecting the input and output pins of the negative polarity of the stabilizer, the input terminal of the positive polarity of the stabilizer connected to the power through the disconnecting element 49,

current shunt 13 current sensor ngt

ruzki 14, collector-emitter of the transistor of the regulating element 1 with the output terminal of the positive field ps14

stabilizer, feedback unit 2 is connected by an output to a control input of a second parallel shunt body 45 and through an isolating resistor 50 to a control input of regulating element 1, and a power output from a connection point of a disconnecting element 49 and a current shunt 15 of a load current sensor 14 , the output of the state of the second parallel shunt element 45 is connected to the first input of the logic element AND 33 and through the delay node 30 to the second input of the trigger-blocking node 20, the first input of which is connected to the output d trigger current load 14 connected by the voltage input to the emitter of the transistor of the regulating element 1, the trigger-blocking node 20 is connected by the power output to the connection point of the tripping element 49 and the current shunt 15 of the load current sensor 14, the blocking output with the control input of the regulating element 1 and the output of the state with the second input of the logic element AND 33, which is connected to the output with the control input of the first parallel shunt element 41, and the power output with the positive output output is stabilized a.

The stabilizer works as follows.

In the stabilization of the output voltage in the absence of emergency modes in the feedback node 2, the operational amplifier 7 compares the voltage proportional to the output voltage of the stabilizer with a reference voltage equal to the stabilization voltage of the Zener diode in the reference voltage source 4. Reference voltage The voltage enters through the second input resistor 11 to the non-inverting input of the operational amplifier 7, to the non-inverted input of which through the first input resistor 10 comes from the output of the output voltage divider 3 (medium the output of the potentiometer is a voltage proportional to the output voltage of the stabilizer. In the source of the reference voltage 4, the required stabilization current of the zener diode 6 is set by the resistor 5 from the output voltage of the stabilizer. Counter-parallel diodes 8 and 9, connected between the inverting., And non-inverting inputs of the operative

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Amplifier 7, as well as the first 10 and second 11 input resistors, form protection across the input of the operational amplifier against dangerous differential and common-mode input voltages. To avoid unstable operation and failures in emergency modes, the power supply of the operational amplifier 7 is derived from the input voltage of the stabilizer through a parametric stabilizer formed by a circuit of series-connected zener diodes 13 and a ballast resistor 12. The voltage value of the supply voltage of the operational amplifier is determined by the voltage of the stabilizer current 13 and - selected less than the nominal value of the voltage of the chip in the allowable

Q limits, which increases the reliability of the operational amplifier and increases the uptime by an order of magnitude. Operational amplifier 7 generates a mismatch signal which

5 of the output of the feedback node 2 is fed through the isolating resistor 50 to the control input of the regulating element 1, stabilizing the output voltage. At the same time

0, the signal from the output of the feedback node 2 is fed directly to the control input of the second parallel shunt element 45, where through a resistor 48 it applies to the base of transistor 47. In the stabilization mode, the positive base-emitter voltage of transistor 47 keeps it in the locked state.

In stabilizer overload mode

Q current over current sensor load 14 through the trigger-blocking node 20 closes the regulating element 1 with a latch, limiting the load current to zero. Correction is performed.

from the current installation of the load current sensor 14 by the voltage drop on the regulating element 1. The output signal from the load current sensor 14 is supplied to the first input of the trigger-blocking node 20, where it is supplied through the resistor 22 and the anode-cathode 26 to the LED diode 28 As a result, a current flows through the LED 28, limited by the resistance value

a resistor 23. The radiation flux of the light emitting diode 28 affects the photo-thyristor 29 (the LED 28 and the photo-thyristor 29 can be implemented as opto-thyristors), which turns on

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and through the photothyristor 29 and the resistor 25 begins to flow current. The voltage drop from the fourth resistor 25 is applied to the output of the state of the trigger-blocking node 20 and. at the same time, through the third resistor 24 to the base-emitter junction of transistor 21, a current flows, which leads to saturation of the transistor 21. At the same time, the Q output of the blocking trigger node 20 receives a potential close to the potential of the common power supply bus (different in voltage Nastipresti collector-emitter transistor | 5 resistor 21). From the blocking output of the trigger-blocking node 20, a low potential is fed to the control input of the regulating element 1 and closes it, thus limiting the overload current (short circuit current). The presence at the second input of the trigger-blocking node 20 of the signal (the following case is given.), Which through the second diode 27 enters the anode of the LED 28, also triggers the trigger-blocking node 20, a low signal level (equal to the potential common power bus) at the first or second outputs of the element I (or at both inputs), respectively, through the first 34 or second 35 diodes blocks the supply of the unlocking potential to the base of the transistor, 40 from the output terminal of the element And through the first resistor 37 and the diode 36. At the same time, transit The stop 40 is closed, and at the output of the element I, whose state is determined by the voltage drop on Q by the third resistor 39, there is no output signal. In this case, the third diode 36 and the second resistor 38 compensate for the voltage drop on the first 34 or second 35 diodes, reliably preventing the unlocking of the transistor 40. If there are high signal levels, the first and second 34

The second 35 diodes are locked and the current flowing through the first resistor 37 begins to flow through the third diode 36 and the base of the transistor 40. As a result, the transistor 40 goes into a saturation state and a high level of the output signal appears at the output of the logic element 33. If the output voltage of the stabilizer is higher than the nominal voltage (for example,).

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an overvoltage on the power buses when operating on a pulsed load, the feedback node 2, seeks to reduce the output voltage to the nominal, produces an output error signal that locks the control element 1. At the same time, from the output of the feedback node, this signal goes to the control input the second parallel shunt element 45, where through the resistor 48 enters. to the base of the transistor 47. In this case, the voltage applied to the base and the emitter of the transistor 47 is unlocking, with the result that the transistor 47 goes into a saturation state, shunt the output of the stabilizer and lowers the output voltage to the nominal the feedback node 2 unlocks the regulating element 1 and locks the second parallel shunt element 45). The collector current of transistor 47 is limited at an acceptable level by resistor 46, the voltage drop on which goes to the output of the state of the second parallel shunt element 45. A high signal from the output of the state of the second parallel shunt element 45 is fed to the input of the delay node 30, the output of which is connected to the second input of the trigger-blocking node 20. With an overvoltage pulse duration shorter than the delay time, the voltage at the output of the delay node will not be sufficient to trigger the trigger blocking node 20. During prolonged overvoltage, the voltage at the output of the delay node triggers the trigger-blocking node 20, which locks the regulating element 1. At the same time, from the outputs of the trigger-blocking node and the second parallel shunt element 45, signals with a high level arrive to the first and second outputs of the logic element AND 33. As a result, a signal is generated at the output of the last, which is fed to the control input of the first parallel shunt element 41, where The resistor 44, which limits the current in the control circuit, is applied to the thyristor control terminal 43. The thyristor 43 opens and, through current limiting resistor 42, shunts the output of the stabilizer, reducing the voltage on the load supply busses to almost zero. The power of the first parallel shunt element 41 is significantly greater than the power of the second parallel shunt element 45, which is designed only for pulsed current. In this case, the overcurrent mode in the power busses of the stabilizer is absent, since the regulating element 1 is locked by the trigger-blocking node 20. In the case of the failure of the regulating element 1, the voltage at the output of the stabilizer begins to increase, which leads to the unlocking of the feedback link 2 of the second parallel shunt element 45. At the same time, the magnitude of the current flowing through the current shunt 15 increases, which causes the load current sensor 14 to be triggered and, consequently, the trigger-blocking node 20 time. In this case, the signal from the outputs of the state of the second parallel shunt element 45 and the trigger-blocking node 20 goes to the first and second inputs of the logic element 33, which includes the first parallel shunt element 41. As a result, the output of the stabilizer without time delay is short-circuited by a powerful first parallel shunt element that creates a mode close to a short circuit, which leads to a decrease in the output voltage below the nominal and the triggering of the tripping element 49 (in this case, Fusible insert arrangement) f This thereby eliminates overvoltage at the stabilizer output with high speed. The presence of the AND 33 logic element allows unlocking the first parallel shunt element 41 only with signals from the outputs of the state of the second parallel shunt element 45 and the trigger-blocking node 20. This ensures the immunity of protection during short-term overvoltages, since the trigger-blocking node triggered with a time delay. However, during the breakdown of the regulating element 1 trigger-blocking node 20 CPA0

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bathes almost instantly. Thus, in this case, the first parallel shunt element 41 is switched on with high speed, which increases the protection accuracy. Direct control of the second parallel shunt element 45 from the feedback unit provides for limiting the overvoltage at the output of the stabilizer with high accuracy at the nominal level. There is no overvoltage protection setting, which significantly simplifies the operation of the stabilizer.

Claims (1)

Invention Formula A DC voltage regulator with overvoltage protection, containing a regulating element connected to one of the power buses, a feedback node, an input connected to the output terminals, and an output to the control input of the regulating element, the first parallel shunt element connected by power leads to output pins, a switching element connected in series with the regulating element, a trigger-blocking node, a blocking output connected to the control input of the regulating element, a current sensor load, output connected to the first input of the trigger-blocking node delay node, characterized in that, in order to improve accuracy and noise immunity while simplifying the overvoltage protection setup, the second parallel shunt element is inserted, the power terminals of which are connected to the output terminals , the control input is connected to the output of the feedback node, and the state output is connected through the delay node to the second input of the trigger-lock node, the logic element which is the first input of the connection n a yield state second parallel shunt element, a second input connected to the output state of the trigger-locking unit and output - to the control input of the first parallel shunt element. ГЩг / п г-п -fs4 + ttH -H