SU1492482A2 - Device for monitoring the alternation sequence of analog signals - Google Patents

Abstract

The invention relates to telecommunications and can be used in control devices of communication systems. The purpose of the invention is to expand the functionality. The device for controlling the sequence of alternating analog signals contains processing units 1 analog signal, each consisting of AND-NOT 2 and 3, AND-NOT 4, display unit 5, r-r 6 pulses and fixing blocks 7 of pulsed signal, each consisting of flip-flops 8, keys 9 and comparators 10. The goal is achieved by ensuring the control of the sequence of alternation of pulse signals with the help of entered fixation blocks 7. 1 sludge.

Description

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The invention relates to telecommunications, can be used in control devices of communication systems, in automation, computer technology and is an improvement of the device according to the authors. St. N 1099394.

The purpose of the invention is to enhance the functionality by ensuring the control of the sequence of alternating pulsed signals.

The drawing shows a structural electrical circuit of the proposed device.

The device for controlling the sequence of alternating analog signals contains blocks 1-1 1-N processing an analog signal, including the first and second elements AND-NOT 2-1 - 2-N and 3-1 - 3-N, the third elements AND-NOT 4- 1 - 4-N, a display unit 5, a generator of 6 pulses and blocks 7-1 to 7-N of a pulse signal fixation, including triggers 8-1 to 8-N, keys 9-1 to 9-N and comparators 10-1 - 10-n.

The device works as follows.

In the initial state at the inputs

C1 - CN blocks 7-1 - 7-N of the pulse signal fixation; low level signals are present. Therefore, in the initial state, the triggers 8 of the pulsed signal fixing unit 7 are reset. The low level signals come from the outputs of the flip-flops 8 to the first inputs of the first and second elements AND-NOT 2 and 3 on the outputs of which high-level signals are set. These signals are fed to the inputs of the third elements AND-NOT 4, the outputs of which are set to low-level signals that do not cause the indication to turn on in block 5. These same signals open the keys 9 in the pulsed signal fixation blocks 7, preparing the fixation blocks 7 to work.

The states of the first and second inputs of the comparators 10 are the same, since the low levels of the signals are present at the inputs and outputs of the flip-flops 8, therefore the outputs of the comparators 10 are low and recording in the flip-flops 8 does not occur. When a high level signal arrives at the C1 input, the state of the inputs of the comparator 10-1 becomes different;

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a high signal, which, through the public key 9-1, enters the trigger input of the trigger 8-1, which leads to a change in the state of its output to unity. This signal is fed to the first inputs of the first and second elements AND-NOT 2-1 and 3-1. The first element AND-NOT 2-1 switches to the zero state, which leads to switching the output of the third element AND-FIE 4-1 to one and switching on the first indicator of the block 5. Signal from the output of the third element AND II, 4-1 closes the key 9-1, which prevents a further change in the state of the trigger 8-1. In this case, a high level of voltage at the second input of the first element AND-NOT 2-2 prepares it for operation. When a high level signal appears at input C2, the circuit operates in a similar way, and the second indicator of the display unit 5 lights up.

Thus, when a given sequence of signals arrives, the corresponding indicators of the display unit 5 sequentially light up. When a signal is interleaved from a controlled sequence of signals, for example, at input C1, the state of the trigger 8-1 remains zero, the first AND-NOT elements 2-1 and 2-2 and the second AND-NOT element 3-1 do not change their state the account of the presence at their inputs of a low level with the output of the trigger 8-1. The third element AND-NOT 4-1 due to the presence of high voltage levels at its inputs remains in the zero state, and the corresponding 1st indicator connected to its output does not light up.

When a high level signal arrives at input 02, the state of the inputs of comparator 10-2 becomes different, its status changes to one, and through a public key 9-2, this signal switches the trigger 8-2 to one. The signal from the output of the trigger 8-2 is fed to the first inputs of the first and second elements AND NOT 2-2 and 3-2. The second element AND-NOT 3-2 of the analog signal processing unit 1-2 opens and passes nee. frequency impulses from the generator output 6 pulses to the first input of the third element AND-NOT 4-2, and the first

I-PE element 2-2 remains in one state due to the low level of the missed signal. The output of the third element I-11E 4-2 of the analog signal processing unit 1-2 changes its state with a frequency of 6 pulses, which causes the second indicator of the display unit 5 to blink, thus signaling a pre-broadcast signal from the specified sequence. In this case, the key 9-1 is periodically opened, which does not allow to finally fix the violation of the specified sequence, in order to exclude the cases of the recovery failing of the required sequence of alternating signals. When any signals fall out of a predetermined sequence, the violation in the sequence of alternation of signals is determined by flashing with the frequency of the low-frequency generator 6 indicators of block 5, corresponding to the place of violation of the alternation of signals. The resetting of the device is carried out by applying low level signals to the inputs C1-CN.

Claims (1)

Claims of Invention: Ustro) 1CT} and for controlling the sequence of alternating analog signals per aut. St. No. 1099394, about j and in particular so that, in order to expand the functionality by providing control over the interlacing of the pulse signals, N blocks of fixing the pulse signal, each of which contains a series-connected comparator, a key and a trigger, are inserted, The signal input of which is connected to the first input of the comparator and is one of the signal inputs of the device and the first input of the fixation unit of the pulse signal, the second input and output of which are respectively the second key input and the output a trigger connected to the second input of the comparator, while the second input and the output of each block of fixation of the pulse signal are connected respectively to the output of the corresponding third I-PE element and to the first input of the corresponding processing block of the analog signal.