SU1485309A1 - Analog memory - Google Patents

Description

The invention relates to analog computing and can be used in analog-to-digital converters. The purpose of the invention to improve the performance of the device. This goal is achieved by the fact that the key element 3 is made sturdy •, resulting in reduced sampling time and the error of the input signal in storage mode on the element 9 of a small capacity, and the implementation of the key element 4 low current makes it possible to compensate for the error from switching element 3 after closing last one. 2 Il.

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The invention relates to analog computing and can be used in analog-to-digital converters. $

The purpose of the invention is to increase the speed of the device.

Figure 1 presents the scheme of the proposed device; figure 2 - timing charts of the device. Yu

The device contains a voltage follower 1, an operational amplifier 2, the first 3 and the second 4 key elements made according to the diode-bridge circuit, the first - the fourth sources 5–8 of the current, the storage element 9 on the capacitor, the control elements 10–13 and the limiting a diode element 14 * current-generating element 15 and an inverse-coupling element 16 on resistors, a block 17 of formers 18 to 21 control signals.

The device works as follows. 25

In the sampling mode, the control signals and <, and ¢, C 5, id correspond to such TTL levels, at which elements 10–13 C are closed and currents flow through elements 3 and 4, charging element 9. This also monitors the output voltage of the device at his entrance.

When the doric levels of the control signals i4, u, i _} , ip} _{5 are} changed to opposite, elements 10 and 11 first open and the diodes of element 3 close, then after some time sd ₀₈ , elements 12 and 13 open and the element diodes close. 4, while the device enters the storage mode.

Choosing 1 | <= 1 _? - 1d can

provide fast sampling at the expense of 45 high currents of element 3 and a small switching error due to small currents of element 4, which turns off after time Gd ₀₈ . During the time Gd ₀₃ , the charging of the element 9 by the current 50 of the element 4 takes place, which significantly reduces the switching error caused by the switching off of the element 3. The total sampling time of the device is

55

+ К _М - С _м 1п

where ive) C. _I dx _c "max input

• zh <·

analog storage voltage;

1kl - the current element 3;

Milestone - input impedance

devices;

- temperature potential equal to 25 mV at ~ 20 ° С;

$ - permissible error _; sampling device. ·

The expression describes two charge cycles of element 9: the first term is a linear charge, and the second term is exponential. The linear charge of the storage capacity occurs until the difference between the input and output voltages of the device exceeds 60 mV. The unbalance voltage υ _{ραί6 of} element 3 also exceeds 60 mV, while the current flowing through the window from the arms of element 3, which charges element 9, will be greater than 0.8 1 _KA , and until _{Pa8 &} becomes 60 mV, the output voltage changes at a constant rate. With a further decrease in the voltage unbalance element 3 so the charge element 9 decreases exponentially.

The implementation of element 4 low current makes it possible to compensate for the error of switching element 3 after the latter is closed.

Claims (2)

Claim Analog storage device containing a voltage follower, an operational amplifier, first and second control signal drivers, first and second current sources, first and second control elements, and a diode limiting element, current-generating element and feedback element on resistors} first key element made according to the diode-bridge circuit, a cumulative element on a capacitor, the first terminal of which is connected to the information output of the first key element and the inverting input of the operating amplifier, and the second - to a first terminal of a feedback resistor element and the output of the operational amplifier and a data output device, a non-inverting input of the operational amplifier five 1485309 6 connected to the zero potential bus of the device; the second output of the feedback element resistor is connected to the output of the limiting element, the voltage follower input and the first output of the current-generating element resistor whose second output is the information input of the device; the output of the voltage follower is connected to the information input of the first key element element, the first control input of which is connected to the output of the first current source and the anode of the diode of the first control element, the cathode of which is connected to the output The first control signal driver, whose input is the first control input of the device, the second control input of the first key element is connected to the output of the second current source and the diode cathode of the second control element, the anode of which is connected to the output of the second control driver, which is the second control input of the device, characterized in that, with " in order to improve the device performance, the third and fourth current sources, the third and fourth control elements on the diodes, the third and fourth drivers of control signals, the second key element made on the diode-bridge circuit, information input and output of which are connected respectively to the output of the repeater are entered into it voltage and inverting input of an operational amplifier; the anode of the third control element is connected to the output of the third current source — and the first control input of the second key element, a second control input of which is connected to the output of the fourth current source and the cathode of the diode of the fourth control element, a cathode of the third diode and the anode of the fourth diode are connected control elements, respectively. to the outputs of the third and fourth drivers control signals, the inputs of which are respectively the third and fourth control inputs of the device. 1485309 2ί one at "H (0 21 e.