SU1483659A1 - Device for establishing communication in multi-channel digital communication system - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase speed. The device contains 1 channel identifier, 2 signal analyzer, transmit and receive switches 3 and 4, decoder 5 and 6 outgoing and incoming signals, channel state analyzer 7 and delay block 8. The device operates in four reception modes: a "Call" signal from the subscriber at the outgoing station, the "Call" signal from the channel at the incoming station, the "End call" signal from the subscriber at the outgoing station, the "End call" signal from the channel at the incoming station. The goal is achieved by the introduction of the decoders 5 and 6, the analyzer 7 and the delay block 8. The device according to claims. 2 and 3, the files are characterized by the performance of the analyzer 7 and the delay block 8. 2 Cp f-ly, 3 ill.

Description

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The invention relates to the field of telecommunications and can be used in wired multi-channel digital communication systems.5

The aim of the invention is to increase speed.

FIG. 1 shows a structural electrical circuit of an apparatus for establishing connections in a multi-channel digital communication system; ka fig. 2 is a structural electrical circuit of a channel state analyzer; in fig. 3 is a structural electrical block delay circuit. five

The device comprises a channel identifier 1, a signal analyzer 2, a receive switch 3, a transfer switch 4, a decoder 5 of the outgoing signals, a decoder 6 of the incoming signals, 20, a channel state analyzer 7 and a delay block 8. The analyzer 7 channel states contains from the first to the sixth elements OR 9-14, the first, second and third triggers 15, 16 and 17, 25 and 17, similar to the actions taken when receiving the first to the fourth keys 18-21 me the signal Call, described above.

pulses from the switch 3 output, appearing after signal detection Call, signal confirmation Call in detector 1 and analysis in analyzer 2. The first delay block 22 serves to delay the reset signal of the first trigger 15, so that the second trigger 16 flips first. This is done in order to close the first and third keys 18 and 20 to pass the call confirmation signal from another station through the decoder 6. In the described mode, in the receiving circuit at the outgoing station, the delay element 26 is not turned on and clocked mpulsy enter the transmitting and receiving system blocks without delay.

Signal reception mode Call from a channel at an incoming station.

A signal arriving at the input of the decoder 6 The call performs operations on the first and third triggers, 15

and the first and second blocks 22 and 23 of the delay. Block 8 delay contains the first and second keys 24 and 25, the element 26 of the delay and the element OR 27.

The device for establishing connections in a multichannel digital communication system operates as follows.

Signal reception mode Call from the subscriber at the outgoing station.

The inputs of the decoder 5 receive a call signal, which, through the third element OR 11 of the analyzer 7, sets the third trigger 17 to one state, thereby preparing the second and fourth keys 19 and 21 for opening in the event of a further signal of the end call, the call signal the output of the decoder 5 also enters the third key 20, previously prepared for opening (like the first key 18) with a single signal from the first trigger 15. The output from the third key 20 goes through the fourth element OR 12 to the reset input of the second trigger 16, and through the fifth element OR 13 and the first block 22 - to the reset input of the first trigger 15. From the first 1 output of the second trigger 16, the unit potential prepares for opening the second key 25 of the block 8 to pass through it (through the OR element 27) corresponding to them

and 17, similar to the effects of receiving the Call signal described above.

pulses from the switch 3 output, appearing after signal detection Call, signal confirmation Call in detector 1 and analysis in analyzer 2. The first delay block 22 serves to delay the reset signal of the first trigger 15, so that the second trigger 16 flips first. This is done in order to close the first and third keys 18 and 20 to pass the call confirmation signal from another station through the decoder 6. In the described mode, in the receiving circuit at the outgoing station, the delay element 26 is not turned on and clocked mpulsy enter the transmitting and receiving system blocks without delay.

Signal reception mode Call from a channel at an incoming station.

A signal arriving at the input of the decoder 6 The call performs operations on the first and third triggers, 15

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The action on the second trigger 16 is the opposite; signal The call from the output of the decoder 6 through the first key 18 and the second element OR 10 is fed to the installation input of the second trigger 16. The second trigger 16 sets a single potential at its second output, preparing for opening the first key 24 of the unit 8.

In this mode, in the receiving circuit at the incoming station, the delay element 26 is turned on and the clock pulses enter the transmitter unit of the switch 4 output without delay, and the system receive block of the switch re-1 switch 3 with a time delay.

Signal reception mode: Hang up from the subscriber at the outgoing station.

From the second output of the analyzer 2 (the first output of the decoder 28) the hang-up signal is received through the third input of the analyzer 7, the second key 19 and the fourth element OR 12 open (the third trigger 17), and the second switch 25 prepares for opening. also performs the following actions: through the first element OR 9 sets the first trigger 15 to one state, preparing the first for opening, and the third keys 18 and 20: resets the third trigger 17 to O (through the third element OR 11 and the block

23), closing the keys 13 and 14. In this mode, delay 26 is not included in the receive circuit at the outgoing station.

Signal reception mode The channel is disconnected at the incoming station.

From the third output of the analyzer 2, the end call signal goes through the fourth input of the analyzer 7, the open 4 fourth key 21 and the second element OR 10 to the setup input of the second trigger 16. The first key 24 is prepared for opening. Otherwise, the end of the signal is disconnected described above. In this mode, a delay element 26 is turned on in the receiving circuit at the incoming station.

Claims (3)

1. A device for establishing connections in a multi-channel digital communication system, comprising a serially connected channel identifier and a signal analyzer, the first output of which is connected to the inputs of a transfer switch and a reception switch, characterized in that, in order to improve speed, an outgoing decoder is inserted into it signals, an input signal decoder, a channel state analyzer and a delay unit, the input of which is connected to the output of the transfer switch, and the first and second control inputs of the delay They are connected to the first and second outputs of the channel state analyzer, the first and second inputs to the key and the outputs of the second trigger that are connected to the outputs of the source signal decoder and the signal decoder of the input signals, the first and second inputs of which are pairwise combined respectively with the first DS and the second, third, and fourth inputs are the channel determiner, with the third and fourth inputs of the analyzer —the states of the channels are connected to the second and third outputs of the signal analyzer, respectively. 2. The device according to claim. 2, wherein the channel state analyzer comprises the first OR element, the first trigger, the first key and the second 1 SHI element whose output is 50 55 are, respectively, the first and second outputs of the channel condition analyzer. 3. The device according to claim 1, wherein the block of the support contains, in series, the first key, the element of the charge and the OR element, to the second in which the output of the second is connected, the input of which is combined with the house of the first key and is the input a delay unit, the first and second equalizing inputs of which are the control inputs of the second and first keys, respectively, and the output of the OR element is the output of the delay unit. five 0 five five connected to the first input of the second trigger, connected in series the third element OR, the third trigger, the second key and the fourth element OR, the output of which is connected to the second input of the second trigger, connected in series the third key, the fifth element OR to the first delay unit, the output of which is connected to the second input of the first trigger and the fourth key connected in series, the sixth OR element and the second delay block, the output of which is connected to the second input of the third trigger, the output of which is connected to the first input of the even key, the output of which is connected to the second input of the second element OR, the first input of which is combined with the second input of the fifth element OR, the output of the first trigger is connected to the first input of the third key, the output of which is connected to the second input of the fourth element OR, the first input of which is combined with the second input of the sixth OR element, and the combined first input of the third OR element and the second input of the third key are the first input of the channel state analyzer, the second input of which is the combined second input rows of the first key and third OR gate, a first input of the combined first OR gate and a second input of the second switch are 1 third input analyzer channel state, the fourth input of which are combined second inputs of the first OR gate and the fourth before the key and the outputs of the second trigger ds 0 five are the first and second outputs of the channel state analyzer respectively. 3. The device according to claim 1, wherein the delay unit comprises a first key connected in series, a delay element and an OR element, to the second input of which the output of the second is connected, the input of which is combined with the input of the first key and is the input of the delay unit, first and the second control inputs of which are the control inputs of the second and first keys, respectively, and the output of the OR element is the output of the delay unit.