SU1478298A1 - Digital filter - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to reduce the distortion associated with the superposition of the spectra of sampled signals. The digital filter contains ADC 1, clock rc 2, adders 3 and 12, switches 4 and 8, shift registers 5, delay block 6, multipliers 7 and 11, coefficient memory block 9, and signal change rate estimation block 10. The goal is achieved by expanding along the frequency axis of the periodic components of the spectra of the input and output signals, especially in those cases where the rate of change of the input signal is large and its main energy is concentrated in the relatively high-frequency part of the spectrum, which requires expansion of the filter bandwidth. This filter uses an adaptive change in the bandwidth depending on the measured value of the rate of change of the signal characterizing its spectral structure. 5 il.

Description

1

a shift equal to the sampling period T,;, the transfer function H, (Z) of the digital filter is equal to

. Z4№

where z ejli L

The transfer function of a digital filter in the frequency domain can be obtained by substituting

Jl Jj-L-in (1): (2)

The invention relates to computing and can be used as part of systems for the transmission and processing of discrete information, c. electric communication, hydro and radiolocation 5, etc. for digital filtering of electrical signals.

The aim of the invention is to reduce the distortion associated with the superposition of the spectra of the sampled signals. JO

FIG. 1 shows the structural electrical circuit of the digital filter; in fig. 2 shows an example of performing a signal speed estimator; in FIG. 3, a time diagram explaining the operation of the 15-1.5-5. The offset is KTD of the digital filter; in fig. 4 and 5 - (K is an integer), then the operator r is the examples of the implementation of the clock generator and the delay unit, respectively.

The digital filter contains an analog-to-digital converter (ADC) 1, a so-called secondary generator 2, the first adder 3, the first switch 4, the shift register, and additional registers 5.1–5.

shift, delay unit 6, first smart- -, increasing the clock frequency of the digitizer 7, second switch 8, block 9 “„ „„ „t„ „„ „„ „„

the memory of coefficients, unit 10 for estimating the rate of change of the signal, the second multiplier 11 and the second adder 12.

Block 10 contains a register of 13 sdvil. . ., elcium of the same kind from that range, elements of 14.1–14t delay, calculating the value of

tateli 15.1-15p, adder 16, threshold blocks 17.1-17K.

The clock generator 2 contains the generator 18, the first switch 19, the block 20 of the frequency dividers and the second 35 switch 21. The block 6 contains the inverter 22 and the D-triggers 23.1-23.2K.

The digital filter works in the following way.

The input signal preliminarily limited in 40 spectra is converted into ADC 1 in digital form, with the sampling rate of the signal in ADC 1

n / itTd.

1-aie If delay is being applied by chain

the shift consisting of the first switch 4, the second switch 8 and the roar (1) must be replaced by z-, in connection with which the new transfer function Hk () is equal to

, . ft "g

„). about)

1-aie

If in this case reduce the sampling period (respectively

and the frequency of the clock oscillator 2) is also K times (xKm), it is obvious that equalities (2) and (3) determine the transfer function of the functionary that in the latter case the distance along the frequency axis between the low frequency region and the left sideband at the first harmonic, the sampling frequency is increased K times for the spectra of the input and output signals by increasing the sampling frequency and the filter clock frequency.

The described separation along the frequency axis of the periodic components of the spectra of the input and output signals is used in the proposed digital filter to reduce the distortion and is determined by the clock frequency shift equal to the sampling period T,;, the transfer function H, the (Z) digital filter is equal to

. Z4№

where z ejli L

The transfer function of a digital filter in the frequency domain can be obtained by substituting

Jl Jj-L-in (1): (2)

n / itTd.

1-aie If delay is being applied by chain

the shift consisting of the first switch 4, the second switch 8 and registers 5.1-5. The offset is KTD (K is an integer), then the operator r

in (1) should be replaced by z-, in connection with which the new transfer function Hk () is equal to

, . ft "g

„). about)

1-aie

If in this case reduce the sampling period (respectively

by increasing the clock frequency of the digital operation „„ „„ „„ t „„ „„ „„ „

and the frequency of the clock generator 2) is also K times (xKm), then it is obvious that equalities (2) and (3) determine the transfer function of the same type with that time, „„ „„ „„ „„ „„

Note that in the latter case, the distance along the axis of their frequencies between the low-frequency region and the left sideband at the first harmonic of the sampling frequency increases by K times for the spectra of the input and output signals by increasing the sampling frequency and the clock frequency of the filter.

The described separation along the frequency axis of the periodic components of the spectra of the input and output signals is used in the proposed digital filter to reduce the distortion

Rattor 2, after which it is applied to the per- fects associated with the effect of the overlap of the adder 3 and the unit 10 for estimating the speed spectra, especially in those cases that increase the signal change. The kind of frequency response of a digital filter is determined by the weighting factors a ,, ag given by

from the coefficient memory unit 9 to the first inputs of the first 7 and second 11 multipliers, and also depends on the speed of change of the input signal and its main energy is concentrated in the relatively high frequency part of the spectrum, which requires expansion of the filter bandwidth.

FA sampling signals in ADC 1, the proposed digital filter is equal to the clock frequency of the digital use of the adaptive change of the wide filter and the defined passband frequency 55 Rinas depending on the oscillator 2. At a fixed rate of x weight coefficients of changes in the signal characterizing the sample and the sampling frequency FA and u its spectral structure. For the relative delay of the signal in the chain of relatively low-frequency signals

the rate of change is small, with increasing frequency it increases. But as the measured rate of change of the signal decreases in the proposed device, the bandwidth decreases accordingly, which provides additional suppression of noise components located in the high-frequency part of the spectrum, and an increase in the signal-to-noise ratio.

The unit 10 for estimating the rate of change of a signal can be constructed, for example, as shown in FIG. 2

When the difference between two adjacent samples is converted into digital form (position code) using K threshold blocks 17.1-17.K, by outputting a signal which, arriving at the control input of block 9 of coefficient memory, causes the weights a, a, determining the frequency response of a digital filter corresponding to the measured value of the sample difference. The structure shown in Fig. 2 at m7l is advantageous to use, for example, if it is known a priori that the useful component of the input signal is concentrated mainly in the low-frequency region, and the noise level in the high-frequency part of the spectrum can be quite large.

In this case, with the measured difference of adjacent samples, as shown in FIG. 4, it can be large even with very low-frequency wanted signals, and due to bandwidth expansion, all high-frequency noise components will reach the output

roystva The use in this case of the structure in FIG. 3 provides averaging of the output signals of the extractors 15.1-15.rn (the adder 16 calculates the sum of the output signals of the extractors 15.1-15 tons, multiplied by hectares 1), and the effect of the high-frequency noise components is less pronounced.

The output signal of the unit 10 for estimating the rate of change of the signal arriving at the control input of the clock generator 2 provides an increase in its frequency if the signal speed is high and a decrease in otherwise

At the same time, the output signal of the unit 10 for estimating the rate of change of the input signal is applied to the control input of the first switch 4, causing

0

five

0

0 days of entry and

connection of the output signal of the first adder 3, and the information input of one of the registers 5,1-5. To shift. The number (K) of the registers 5.1-5. K of the shift included between the switches 4 and 8 determines the number of operating modes of the digital filter corresponding to the number of used sampling frequencies. The lengths of all registers 5.15. To the shift (the number of successively included delay elements in each register) are different and proportional to the values of the sampling frequencies used.

In order to switch the registers 5.15 to the shift, the last of the samples stored in that of the shift registers through which the information passed before the switch was not lost, the switching process of the inputs of the second switch 8 must be delayed by the value of the sampling period with respect to the moment of switching 5 of the outputs of the first switch 4. To this end, the output code of the unit 10 for estimating the rate of change of the signal is delayed before being fed to the control input of the second switch 8 using the delay unit 6 by the period value d sparking.

Thus, the proposed digital filter provides digital filtering of signals, and in order to increase the noise immunity, not only the weights of the digital filter can be changed in accordance with the spectral structure of the input signal, but also the sampling rate of the output from the needles. the invention

five

Formula

A digital filter containing serially connected analog-to-digital converter, whose input is a digital filter input, a first adder and a second adder, whose output is a digital filter output, as well as a clock, shift register, first and second multipliers, memory block These coefficients and a unit for estimating the rate of change of the signal, the input of which is connected to the output of the analog-digital converter, and the output are connected to the input of the coefficient storage unit, the first and second outputs of which are connected to the first inputs of the first and second multipliers, respectively.

the second inputs of which are combined, and the outputs of the first and second multipliers are connected to the second inputs of the first and second adders, respectively, and the clock inputs of the analog-digital converter, the shift register and the unit for estimating the rate of change of the signal are connected to the output of the clock generator, different from that in order to reduce the distortions associated with the superposition of the spectra of the randomized signals, the first and second switches are introduced, K-1 additional shift registers and a delay unit, the output of which is connected to the control second input

Fie.2

switch, and the input of the delay unit is connected to the control input of the clock generator, the output of the rate of change rate of the signal and the control input of the first switch, the input of which is connected to the output of the first adder, and the i-th output of the first switch, where, 2, .. ., K, is connected via the corresponding shift register to the i-th input of the second switch, the output of which is connected to the second inputs of the first multiplier, with the clock inputs of the delay unit and additional shift registers connected to the output of the clock generator.

To the legislative ntstsi 8xotan SAOKO 2.T.6.9

Fig.Z

I

R

go

zr

L then # / gg0Јm entrances b eye 1,5,6,10

Fig4

P

Claims (1)

Claim A digital filter containing a series-connected analog-to-digital converter, the input of which is the input of the digital filter, the first adder and the second adder, the output of which is the output of the digital filter, as well as a clock generator, shift register, first and second multipliers, coefficient memory block and evaluation unit the rate of change of the signal whose input is connected to the output of the analog-to-digital converter, and the output is connected to the input of the coefficient memory block, the first and second outputs of which are connected to the first moves the first and second multipliers respectively. the second inputs of which are combined, and the outputs of the first and second multipliers are connected to the second inputs of the first and second adders, respectively, the clock inputs of the analog-to-digital converter, the shift register, and the unit for estimating the rate of change of the signal are connected to the output of the clock generator, characterized in that, with In order to reduce distortions associated with the imposition of spectra of discriminated signals, the first and second switches, K-1 additional shift registers and a delay unit, the output of which is connected to the control the input of the second switch, and the input of the delay unit is connected to the control input of the clock generator, the output of the unit for estimating the signal change rate and the control input of the first switch, the input of which is connected to the output of the first adder, and the ith output of the first switch, where i = 1 , 2, ..., K. connect (Q nen through the corresponding shift register with the i-th input of the second switch, the output of which is connected to the second inputs of the first multiplier, and the clock inputs of the delay unit and ₁₅ additional shift registers are connected to the output of the clock generator. Fig.Z 1- + 78298 Fie 5