SU1464161A1 - Arrangement for locking and restarting electronic computer in power supply failures - Google Patents

Abstract

The invention relates to computing technology, can be used in digital computing complexes of increased reliability, and is intended to protect information stored in the main memory of a computer when the supply voltage is turned on and off. The purpose of the invention is to increase the reliability of the device operation by ensuring control of not only the mains voltage, but also the voltage of the main power source. The device for blocking and restarting the computer at power failure contains two amplifiers, a trigger, a delay element, a switch, a main and backup power sources, a comparator, an OR element, an AND element, an HE element, and two pulse drivers. New in the device is the inclusion of the comparator, the element And and the element NOT with the specified connections, which allows to control the disappearance of the mains voltage and the voltage of the main power source, to generate the signals of blocking and zoning in the event of a failure in any power supply circuit. , switch to the backup power source, ensure the safety of information in the computer memory about the state of the interrupted computational process, restore the information after turning on the power and continue the calculation process. 2 Il.

Description

one

The invention relates to computing technology, can be used in digital computing complexes of increased reliability, and is intended to protect information stored in computer RAM when the supply voltage is turned on and off.

The purpose of the invention is to increase the reliability of the operation of the device by ensuring control of the main power source.

FIG. 1 is a block diagram of the device; in fig. 2 - time diagrams of his work.

The device contains the first 1 and second 2 pulse shapers, the element OR 3, the backup 4 and the main 5 power sources, switch 6, comparator 7, element AND 8, second amplifier 9, trigger 10, element 11, delay element 12, first amplifier 13 The output 14 of which is the output of the device for connecting the power supply input of the computer, the drives 15 and the device ij6 for connecting the access inhibiting input to the main and the computer interruption input and the input 17 of the monitored primary power supply

The device works as follows

: The shapers 1 and 2 perform one half-period straightening, acting: at the device input 17, a sinusoidal signal (removed, for example; from the secondary winding of the power transformer) j as well as amplification and formation of positive impulses 5 shifted by half ne - | of the period relative to each other KfIGo) which arrive at the 1 INPUT of the element OR 3. The value of 1p of the backup source 4 pita ™ is not a little less than that of the main source 5 (Fig. 2e) „

Under normal network voltage on

a small signal (since on the input of the terminal And 8 it was set O), which passed the delay element 12 (the time of recording data in the computer state memory) resets the trigger 10 to O. The switch 6 triggers off the signal and switches to output 14 connects backup source

10 power, which maintains the storage mode. Simultaneously, the signal O from the output of the trigger 10, the amplifier 13 has passed, forms a zero signal on the course 15 of the device,

15 which blocks access to the memory of a computer.

If during normal voltage, the voltage of the main and the source 5 disappears, then the output of the comparator 7 is zero.

al, at the output of the element And 8 also n is O, which, having passed the amplifier 9, causes interruption of the computer. Power failure, starts

: The output of Element OR 3 (Fig. 2d) is a single microprogram of writing data to a panic signal (since O and 8 were set to O), which went through delay element 12 (the time it takes to write data to the state memory) trigger 10 in O. A signal from the output of trigger 10 turns off switch 6, and a backup source 4 is connected to output 14

power, which maintains the storage mode. At the same time, the signal O from the output of the trigger 10, after the amplifier 13 has passed, forms at the output 15 of the device a zero signal,

which blocks access to the memory of a computer.

If during normal network voltage the voltage of the main source 5 is lost, then the output of the comparator 7 is set to zero potential

a, at the output of the element And 8 also appears O, which, having passed the amplifier 9, causes an interruption of the computer. Power failure, starts

firmware write data in pa

a null signal5 which is fed to an input of an element AND 8, on another input of which is also a single signal from 1 output of the comparator 7 (Fig. 2e), Uni-: a single signal from an output of an element: And 8 .The trigger 10 is set to state 1 and amplifier 9 is allowed to work computer. Single signal from: trigger output 10 through. Amplifier 1 enables those who access the memory unit. And turns on switch 6, to: output 14 of which is connected to: request of the main source 5 "

When the mains voltage drops due to the inertia of the main source 5 (energy j accumulated in the capacitors of the power supply unit coupler), the voltage at its outputs is maintained for some time and then starts (fig 2d). In this period, at the outputs of drivers 1 and 2 and the element of the IPI 3, respectively, is set to zero potential; at the output of element I B (Fig. 2g), O, which passed the amplifier 9, is also set: the signal 0 on the output 16 of the device, the signal 0 processed by the computer, is like.:; ignore interrupt power failure, and a micro-trigger is started to record data about the state of the computer and the programs being run at the time of turning off the mains voltage. At the output of the element NOT 11, one appears.

five

information about the state of the computer. The output of the element 11 is set to 1 and after the time determined by the delay element 12 the trigger 10 is reset, the output signal of which through the amplifier 13 blocks the access to the computer memory block and simultaneously switches off 6, the output 14 of which is energized from the backup 4 power source - neither does storage provide.

After switching on the network, when the nominal value of the alternating voltage is established, output pulses appear at the outputs of drivers 1 and 2 (Fig. 26, c). At the output of the element OR 3, a single signal appears (Fig. 2d), which

is applied to the second input of the element 8. After the nominal value of the voltage of the main power source 5 is established, a single appears at the output of the comparator 7

the signal that arrives at the input of the element FROM, If there are two single signals at the input of the element AND

8 the last one is triggered, and at its output (Fig. 2g) appears 1. By this signal at the output of the amplifier

9 a single signal is set up to allow the computer to work; Simultaneously, the signal from the output of the element 8 sets the trigger 10 to the output

Claims (1)

the signal of which, having passed through the amplifier 13, allows access to the memory block. The output signal of the trigger 10 includes a switch 6, at the output 14 of which the voltage of the main power source will be connected. If there are single signals at the output of amplifiers 9 and 13, enabling the operation of the computer and accessing the memory unit, the state of the computer is restored to the time of power failure and the interrupted computing process continues. Invention Formula A device for blocking and restarting a computer at power failure, containing the first and second pulse shapers, the OR element, the main and backup power sources, the switch, the delay element, the trigger, the first and second amplifiers, the outputs of which are, respectively, the outputs of the device the access of the memory access prohibition and the interrupt input of the computer, the input of the first amplifier is connected to the trigger output, the reset input of which is connected to the output of the delay element, the output of the switch is the output of the device for CONNECTIONS power input computer and is connected to the power supply input trigger backup power supply output is connected to the first five 0 5 o the input of the switch, the second input of which is connected to the output of the main power source and the power inputs of the delay element, the OR element, the first and second pulse formers, the inputs of the pulse formers are combined and are the device input, the outputs of the first and second pulse formers are connected respectively to the first and second inputs element OR, in particular, in order to increase the reliability of the device operation by ensuring control of the main power source, the element NOT and nt and the comparator, the first and second: vhoda1 comparator connected respectively to the outputs of the first and rezervno- main power source, and, the output - to the first input of the AND, the second input of which is connected to the output of the OR gate; the output of the element I is connected to the input of the second amplifier; by the installation input of the trigger and the input of the element NO, the output of which is connected to the input of the delay element, the output of the trigger is connected to the control input of the switch, the output of which is connected to the power input of the first and second amplifiers, the power inputs of the comparator, And element and element are NOT connected to the output of the main power source. T 1