SU1462356A1 - Multichannel correlometer - Google Patents

Abstract

The invention relates to specialized computer hardware and is intended to determine the autocorrelation function of a random process in real time. The purpose of the invention — speed increase — is achieved by analyzing the matches and anti-matches of the samples being analyzed in two consecutive sampling cycles. A correlometer contains a signer shaper 1, two shift registers 2, 3, a synchronization unit 8, a trigger 9 and in each channel three sign multipliers 4-6 and a reversible counter 7. 1 Il.

Description

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 The invention relates to specialized computational tonic tools and is intended to calculate the autocorrelation function of a stationary random process in real time, in particular, in spectral studies in radio astronomy.

A multichannel correlometer containing a sign shaper, whose input is the information input of the correlometer, first shift register, block syn; analysis and N analysis channels, each of which contains the first sign multiplier and reverser of the invention — an increase in the fast counter; the first output

affinity.

i The drawing shows a structural

| Skem correlometer.

The correlometer contains a driver

the synchronization unit is connected to the clock inputs of the reversible counters, the second output of the synchronization unit is connected to the clock input of the first

which is connected to the output of the sign maker, in each channel the output of the first sign multiplier is connected to the countable input of the reverse

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1 character, the first 2 and second 3 registers of the shift register 15, the information input of the shift, the first 4, the second 5, and the third 6 sign multipliers, reversible counters 7, synchronization block 8 and; trigger 9.

 The correlometer works as follows about the counter, the first input of the first sign is 1 time.

  The sign generator 1 forms; the sign analogue of the input signal, the positive and negative signs being encoded with logical ones and zero, respectively. During the four clock cycles, the code is written into the trigger 9, into the next, odd clock cycles, directly into the first digit of the first register 2 and from the trigger 30, the information is rewritten into the first bit of the second register, Z. the shift of all the previous codes by one bit. Gakim way, in the first register 2 of 5 stored codes of the process at odd moments of the sample, and in the second register 3 - at even moments of the sample.

The first multiplier is connected to the output of the first bit of the first shift register, characterized in that, in order to increase speed, a trigger has been entered into it, the second shift register and two sign multipliers in each analysis channel, the sign maker output connected to the trigger information input the input of which is connected to the third output of the synchronization unit, the second output of which is connected to the clock input of the second shift register, whose information input is connected to the forward output of the trigger, the first inputs of the second character each multiplier of each channel is connected to the output of the first bit of the second register

Each channel of the correlometer is nakashti-„shift, in the i-x channels (where i 2, 4,

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is proportional to the coefficient of sign correlation by the equation

1 RCnD) (x,.,. X,. ,,) +

+ sign (x). (1)

The sign multipliers 4 and 5 of each channel form logical products of codes in accordance with the first section.

or the second term in square brackets of equation (1), with the first term defining the direction of counting, and the result of applying to these

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6 / ..) the second inputs of the first and second sign multipliers are connected to the + J output.

the first and second shift registers, in the J-X channels (where j is 1,3,5, ...) the second input of the first sign multiplier is connected to the output

J + 1

raz da

the second shift register, and the second input of the second sign multiplier

connected to the output

Jyz

bit of the first shift register, in each channel the yykhody of the first and second sign

two components of the operation excluding its multipliers are connected respectively II

or in the sign multiplier it is allowed, but to the first and second inputs of the third

If the match multiplier coincides with or prohibits the sign multiplier, the output of which is a mismatch, the count in the reversible count is connected to the input of the resolution of the channel. The count of the reversible counter.

Claims (1)

Invention Formula A multichannel correlometer containing a sign shaper, whose input is the information input of the correlometer, first shift register, block syn; radionization and N analysis channels, each of which contains a first sign multiplier and a reversible counter, with the first output the synchronization unit is connected to the clock inputs of the reversible counters, the second output of the synchronization unit is connected to the clock input of the first shift register information input which is connected to the output of the sign maker, in each channel the output of the first sign multiplier is connected to the countable input of the reverse shift register information input counter, the first input of the first counter, the first input of the first The first multiplier is connected to the output of the first bit of the first shift register, characterized in that, in order to increase speed, a trigger has been entered into it, the second shift register and two sign multipliers in each analysis channel, the sign maker output connected to the trigger information input the input of which is connected to the third output of the synchronization unit, the second output of which is connected to the clock input of the second shift register, whose information input is connected to the forward output of the trigger, the first inputs of the second character each multiplier of each channel is connected to the output of the first bit of the second register shift, in i-x channels (where i 2, 4, 6 / ..) the second inputs of the first and second sign multipliers are connected to the + J output. the first and second shift registers, in the J-X channels (where j is 1,3,5, ...) the second input of the first sign multiplier is connected to the output J + 1 raz da the second shift register, and the second input of the second sign multiplier connected to the output Jyz bit of the first shift register, in each channel the yykhody of the first and second sign