SU145065A1 - Triple counter - Google Patents

Description

There is a known method of constructing a counter from half adders, which are developed in a threefold numbering system. However, the construction of reversible counters in a known manner requires, in the case of subtraction, the simultaneous addition of an additional unit code to all semi-totalizers.

The proposed ternary counter, using successively connected ternary half-adders, does not have this drawback and is characterized in that to ensure reverse operation, the input of the counter is connected to the input of the first half-adder via a switching circuit, the second input of which is connected to the sign bus.

The functional diagram of the described ternary counter (two bits) is shown in the drawing.

The operation of the ternary half-adder, on the basis of which the counter is built, is characterized by table 1.

The first term (.4)

The second term (B) 001 - O- 1-1

Sum011 - 1-10 O-li

Migrating000 | 000, 01

In order for the semi-secondary math controller to perform the functions of a ternary counter, the output “sum 1 is connected to the input“ Л 1, and the output “sum - -1 is connected to the input“ А -1, thus forming on the four upper elements semi-adder ternary dynamic trigger. The ternary counter stage obtained as a result of this connection operates in accordance with Table 2, similar to Table 1 of the half-adder operation.

Initial state, trigger010 I -101

Digit input B00 0-1 - 1

New state trigger 011 i-1 -10

Transfer to the next step .000 OLD 01

Table

table 2

The number of pulses received at the "B 1" input is recorded on the meter triggers as a positive three-fold number. Oodava then impulses to the input “fi -1, you can successively reduce the counter reading to zero and then form a negative number on it. In other words, the reverse in the described counter is carried out by simply switching the inputs, which corresponds to the addition of -I (i.e., subtract one) in this number system. The counter counts the pulses according to their sign, and the sign is determined by which of the inputs received the impulse.

It is possible to apply pulses to the input of the counter by one input ".b 1. In this case, the sign of the pulse must be determined by its polarity.

The described reversible counter can be used in the design of computers with a ternary number system.

Subject invention

A ternary counter using sequentially connected ternary half-adders, characterized in that, in order to ensure reversible operation, the input of the counter is connected to the input of the first half-adder via a switching circuit, the second input of which is connected to the symbol bus.