SU1444890A1 - Matrix storage for read-only memory - Google Patents

Description

No. 46

No. 19, 1976,

(21) 2596715 / 18-24

(22) 31.03.78

(46) 12/15/88. Bul

(72) L.G. Likhatsky, A.T. Yakovlev

and N.A. Kuvarsin

(53) 681.327.27 (088.8)

(56) Electronics, 977,

with. 18-19.

TIER. Per. with. № 7, s, 20-44.

IEEE, Trans, on Electronic Devices, V. ED-24, 1977, No. 5.

US patent No. 3914855, CL 29-571. (54) (57) 1. A MATRIX DRIVE FOR A PERMANENT STORAGE DEVICE, containing a semiconductor substrate, on the surface of which a dielectric layer is located, on the surface of which are mutually intersecting and isolated one from another.

tires made of a conductive layer, characterized in that, in order to understand the degree of integration of the storage device, it contains low-alloyed semiconductor and dielectric areas sequentially located on the surface of the semiconductor substrate in the dielectric layer under corresponding intersections of numerical and discharge buses, numerical tires and dielectric areas are filled with holes filled with a conductive layer of discharge tires.

2. The accumulator according to claim 1, characterized in that the dielectric region is made of two-layer, for example, silicon dioxide with a thickness of 5-2.5 nm and silicon nitride with a thickness of 50-100 nm.

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The invention relates to computing and can be used in the manufacture of integral storage devices.

A matrix accumulator is known in which a single memory element is formed at the intersection of two conductor buses insulated from each other. The matrix storage device contains a low-resistance semiconductor substrate, a semiconductor layer of the same conductivity type with a low impurity concentration, parallel diffusion conducting busses of a different conductivity type. In these

the tires at the same distance from each other have holes in which low resistance regions of the same type of conductivity as the substrate are located at some distance from the edge of the diffusion tires. Other parallel conductive tires are perpendicular to the diffusion, intersect them at the opening above the low-resistance areas and lie on the dielectric coating, which has a thickness of 0.05-0.15 µm above the low-alloyed area. The high-alloy substrate serves as a common drain area for all

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devices. Diffusion tires arranged in parallel are a common stopping area used as discharge tires. Other conductive tires intersecting diffusion tires are numeric tires. At the intersection of these tires and a thin dielectric, the storage capacity of the dynamic memory cell is formed, with the low-ohm region being the source of the memory cell.

A disadvantage of the design of such a matrix accumulator is that, although the cell dimensions are determined by the intersection area of the numeric and bit mHHs, additional area is required to create the source area S lying inside the diffusion bus.

The closest to the present invention is a matrix storage device of a permanent storage device containing a semiconductor substrate, the first conductive layers, which are drains and sources of MIS transistors, over which a dielectric coating is located with local areas of thin dielectric between drain and source areas. The second wires of your layers are located perpendicularly first, lie above the areas of a thin dielectric, forming the gate of a MIS transistor at the site of the thin dielectric. and there may be a hole above the areas, not the gate of the MD11 transistor,

Assigning the creation of interconnects between the drain, source, and gate areas, the cell area of this matrix accumulator is considerably large.

The goal is to improve the integration of the matrix ROM drive.

The last objective is achieved by the fact that the matrix storage device for the ROM, which contains semiconductors on the substrate, is located on the surface of which a electrical layer, on the edge of which are isolated from each other numerical and discharge buses that are made of a conductive layer, areas are entered low alloy semiconductor and dielectric region; successively located on the surface of the semiconductor substrate in the dielectric layer under the corresponding intersections of the number and bit buses, the number spaces and areas of the dielectric being made with openings filled with a conductive layer of the number bits.

In addition, to ensure multiple information recording, the dielectric region is filled with a two-layer,

for example, from silicon dioxide with a thickness of 1.5-2.5 them and silicon nitride with a thickness of 50-100 nm.

FIG. shows the design of the matrix accumulator; in fig. 2, section A-A in FIG. one; in fig. 3, the reprogrammable memory cell design in FIG. 4 - electrical circuit.

Matrix drive contains

low impedance semiconductor substrate 1 (common drain of all transistors), dielectric layer 2, low alloyed regions of semiconductor 3 (channel regions of transistors), dielectric regions 4, conductive strips 5, which are numerical buses (common gate of transistors), insulated by dielectric 6 from them wire bands 7,

being bit-wound (buses connecting the drains) and connected in region 8 (drain of a separate transistor) with semiconductor regions 3 or lying in region 9

on the dielectric layer 2.

The memory element is formed at the intersection of numeric 5 and bit 7 tires. To ensure multiple information recording, the dielectric area is double-layered (4a, 46, fig. 2)

An example. The matrix drive contains a silicon substrate with

a volume resistance of 0.01 ohm "cm, thickness 350 μm, a dielectric layer of SiO, 1.5 μm thick, a semiconductor Si region with a volume resistance of 100 Ohm.cm thickness

 µm, numerical and discharge buses in the form of strips of poly-Si 0.5 µm thick with a surface resistance of 30 Ω / cm, isolated from each other by a SiOg layer 0.2 µm thick,

dielectric areas of SiOg. 0.1 µm thick, with the conductive strips being numerical and the dielectric areas made with 1.5 µm holes that are filled with a conductive layer of discharge tires.

The information is read off by applying the potential to the numerical bus (Fig. 4.). Depending on this potential, a voltage corresponding to 0 or 1 is applied to the amplifier. selecting a memory cell simultaneously applies voltage to tires 5 and 7. The unselected memory cell corresponding to the state has a maximum resistance corresponding to the condition of complete integration of the transistor channel (about 10 ohms). For this, bus 5 maintains a zero voltage. The resistance from the memory cell corresponding to the state O is much greater regardless of the voltage at 5 bus, since this is the resistance of an oxide layer about 1.5 µm thick.

In the case of coupling 1 to bus 5, a voltage of 5 V is applied, transferring a layer of silicon under this bus to the enrichment mode and reducing the resistance of this layer to 1 ohm. At the same time, the load must have a resistance 5–0 times more so that the load resistance — an open transistor — is processed on the resulting divider, the voltage level corresponding to 1. The noise immunity condition of such a matrix can be expressed by the following inequality:

tau 7 and m 1 and m

or

R

  lOR, - m

Rn 1ok., Ъ

R

viaif

10 R

m 1 0

fni ri

where m is the number of cells on the bus,

those. when on bus 7 all cells 1,

except one 0 - 5 dL

0 5 0

° 0 5

0

five

Eliminate false counts. when reading 0 - cells, it is necessary to limit the maximum number of cells on the bus 7. In our case, ha Y.

When ensuring multiple recordings, information is stored as a charge at the interface of two dielectric layers,

Information is recorded in the selected cell by applying a threshold recording voltage (about 15 V) to bus 5, and zero voltage to bus 7. In order to avoid writing to all the other cells of the bus 5, all the other buses 7 are supplied with a voltage of about 5V j, which j MeHb is the potential difference between the gate bus and the substrate. In this case, the dielectric interface is charged with such a quantity of charge that it corresponds to a voltage of about 5V.

When counted, buses 5 apply a zero voltage, which puts cells with an uncharged dielectric in the state with maximum resistance, and cells with a charged dielectric in the state with minimal resistance. All other tires 5 are supplied with a voltage of 5V.

The matrix drive allows you to create a ROM with the size of the storage element of no more than I O micron with a sampling time of no more than 10 and a low power consumption. Such a high speed is obtained due to the higher mobility obtained in the configuration with perpendicular current, where the carriers move in the mass of silicon rather than along the surface, as in standard MOS devices.

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Claims (1)

1. MATRIX STORAGE FOR A PERMANENT MEMORY DEVICE, containing a semiconductor substrate, on the surface of which there is a dielectric layer, on the surface of which are numerical and bit mutually intersecting and isolated from one another