SU1444801A1 - Device for shaping trains of discrete-frequency signals - Google Patents

Abstract

The invention relates to computing and can be used in the technique of forming discrete-frequency signal sequences. The aim of the invention is to improve the speed of the device based on the accelerated formation of a multiplicative group. Accelerated formation of elements of the multiplicative group of the Guld field GF (PJ) is carried out due to the newly introduced second counter 6, trigger 7, first and second groups of elements AND 8, 9, -9m, group of elements OR, block adders modulo two 11. In addition The device contains a counter 1, a residual shaper 2, a register 3 a multiplier 4, a block for outputting discrete frequency signals 5. 1 Il. with

Description

(L

The invention relates to supervisory technology and can be used in the technique of forming discrete-frequency sequences: signals carrying in their structure a greater degree of uncertainty about the form of the waveform, the duration of the signals and their ensemble characteristics.

The aim of the invention is to improve the speed of the device during the formation of the multiplicative group: Indeed, to form a discrete-frequency signal sequence, it is necessary to build a multiplicative field group GF (pp having the form a, b (mod p O; a 7 Q f (mod p.))

and PI

(mod p;)

Where

 primitive element of the floor GF (Pi);

R; - module FIELD,

To obtain each number-element of the multiplicative group in the Prototype Device, the previous number-element a is cleared to the primitive element in, the floor GF (p.)

a - b

and J a 5 e; (mod p), X (mod p.

Thus, to form the multiplicative group of the field GF (p,. You need a time T equal to

a 1 a, 6; (mod p),

. an a., 6; X

t, p,

(one)

Where

AT

. T,

the time required to form a single element number of the multiplicative group of the field GF (p;). same time from number theory from

one

aecTHOj what a y, + -

It can be calculated by. formula

pi + 1

al + p i - a.

element

It is known that during the time of multiplying a „element by a primitive element 9; a subtraction operation can be performed. Thus, when the operation is realized in the device. (2) the gain in speed is achieved.

The drawing shows the functional electrical circuit of the device.

The device contains the first counter 1, the shaper 2 residues, register 3, the multiplier 4, block 5 with discrete-frequency signals,

0

five

0

five

0

five

ABOUT

five

0

five

the second counter is 6, trigger 7, the first group of elements is AND, where ha is the dimension of the code of the element of the multiplicative group, the second group of elements is AND 9, -9, the group of elements OR, block 11 modulo-two adders.

The device works as follows.

Initially, the second counter 6 is in the zero state, and the trigger 7 is in the unit state (one is in effect on the inverse output).

Before starting the operation, multiplexer 4 records the binary code of the primitive element number b of the corresponding field GF (p;) and the code of the number P; elements of the floor GF (p.)

Applying a pulse Starting the inputs to the start of the multiplier 4 and the block of discrete-frequency signals 5, the device is put into operation, on the basis of this pulse, the block issuing discrete-frequency signals 5 starts issuing clock pulses on its clock output. Based on the pulse data, the multiplier multiplies 9 by one, and at the end of the multiplication, at its output, sets the pulse to its initial state on counter 1 and register 3 and then, at each clock point, the multiplication result code is output to shaper 2. Shaper 2 generates the remainder of the number modulo p and outputs the result to register 3. The latter carries the remainder modulo the outputs of the multiplier 4. This remainder is the result of multiplying the unit by 8; modulo p, and is the first element of the multiplicative Galois field group GF (p.). The multiplier 4 outputs the first element and to the inputs of block 5 through the open elements AND of the first group of elements AND and the elements IL 10−10. At the same time, in binary code it arrives at the first input of the block 11 modulo two, to the second input of which the code of the number p; In block 11 modulo-two adders, one-bit summation of binary numbers without transfer occurs, which corresponds to subtracting the number a from p.

Trigger 7 under the influence of a pulse from counter 6, which counts modulo K, where K is the number of ticks.

31 /,

necessary to perform the multiplication and determine the remainder modulo p., goes into the zero state (at the first output O, and at the second inverse, 1) and locks the group of elements AND 8-8 | "and opens the second group of elements AND 9i-9 , Through the open group of the elements AND, „and the elements OR the code of the number a (p. 1) / 2 + n is fed to the information input of the block 5 of the distribution of discrete o-frequency signals. The End Multiplication signal from the output of the multiplier 4 sets trigger 7 to one state, and counter 1 and register 3 to zero. In the multiplier 4, at the next stage, the multiplication of the Galois element by the transformed element 6 occurs ;. Then the specified cycle of operations is repeated and the second and (p, .- 1) / / 2-2 elements of the multiplicative group of the GF field (p.), Etc. are formed. Thus, at the input of a block of discrete-frequency signals, a sequence of residual codes appears a j a p ,, / 2 + 1; and p., / 2 + 2, -, and p, / 2 + p. This sequence of parallel binary residual codes is a sequence of emails of the multiplicative group of the field GF (p;).

The sequence of parapel binary codes of the residuals goes to E block 5, where the formation of complex signals takes place in accordance with the information of the module p;.

The positive effect when using this device is that due to the increased speed it is possible to generate signals with a large number of elements in the same time. The latter leads to a gain in the quality of information transfer under the conditions of deliberate fields.

Claims (1)

Formula from b reteni A device for generating sequences of discrete-frequency signals comprising a first counter, a residual generator, a register, a multiplier, a distribution unit of discrete frequency signals, the output of the counter bits connected by the first information input of the residual generator, the output of which is connected to the information input of the register, pa /. the parallel output of the register data is connected to the second information input of the remainder generator and the multiplier input of the same name, the output of the multiplication end prize is connected to the reset inputs of the register and the first counter; signal of the discrete-frequency signal output unit is connected to the synchronization inputs of the multiplier and the register 5 and the counting input of the first counter, the start input of the multiplier is connected to the same input of the block as discrete-frequency signals and ow. The device start input, the inputs of specifying the code of the signal of the primitive element and the code of the number of elements of the Galois field of the multiplier are the corresponding inputs of the same device, different 25 by the fact that, in order to increase the speed of the device during the formation of the multiplicative group, the second counter, trigger, first and second groups of elements I, the group 2Q elements OR, a block of adders on Md-two, and the counting input of the second counter is connected to the clock output of the discrete-frequency signals block, the overflow output of the second counter is connected to the trigger reset input, the installation input of which is connected to the output of the end of multiplication sign. multiplier, the direct output of the trigger is connected to the first inputs of elements AND of the second group, and the inverse output is connected to the first inputs of elements AND of the first group, the second inputs of which are connected to the output of the result multiplier and bit of the first input of the block of adders modulo two, the outputs of the block of adders modulo two are connected to the second inputs of the AND elements of the second group, the outputs of the AND elements of the first and second groups are connected respectively to the first and second inputs of the HW group of the outputs of which are connected to the Dami information input unit discrete-frequency 35 40 45 50 55 signals, bits of the second input of the block of adders modulo two are connected to the inputs of specifying a code for the number of elements of the Gapua multiplier floor.