SU1439679A1 - Solid-state direct-access memory with data correction - Google Patents

Abstract

The invention relates to computing, in particular, to .- integrated semiconductor storage devices. The purpose of the invention is to simplify the device. Arrange

Description

J3; g 8.9 -SETO.

(L

with

 с со о со со

The device contains a drive 5 with cells 1 of the memory of information bits and cells 2 of the memory of control bits combined into groups, for example, byte, decoder 3 addresses, address amplifiers 4, correction blocks 10, element OR 11, elements 12 and 13 delays. In the process of recording, a check reading of the information is made in the correction blocks 10 and the read and recorded information is compared in them. In case of an error, the information is written repeatedly, but in inverse1

The invention relates to computing, in particular to integrated semiconductor memory devices.

The purpose of the invention is to simplify the device.

The drawing shows a structural diagram of the proposed device.

The device contains 1 memory cells of information bits of the accumulator, cells 2 memory of the control bits of the accumulator, decoder 3 addresses, address amplifiers 4, memory 5, information inputs 6 and outputs 7, write resolution 8 and read 9, correction blocks 10 element IDN 11, the first 12 and second 3 delay elements

Each correction block 10 contains a check bit writing block 14, Negligence elements 35, information bit read blocks 16, a J7 block read block, elements of J8 inequality, a compare block J9, information registers 20, check data registers 21, the element And 22 and YPI 23 and blocks 24 of the information recording.

Comparison block J9 contains the elements Inequivalence 25 and .I 26.

The device works as follows.

The address signals from the inputs of the decoder 3 are fed to the inputs of the amplifiers 4 and the address transistors of the selected 3 decoder 3 cells 1 and 2 open.

in the cell 2 of the control bit of the corresponding group of bits of the accumulator, the Log signal is recorded, and when read, the data is inverted. In this way, one-bit bugs in each group of bits (byte) of drive 5 are fixed. Simplification of the device is achieved by reducing the number of address amplifiers 4 by connecting the output of each of them to the inputs of the memory cells of the same name of different groups (bytes), 1 Il.

Information signals from inputs 6 through Negligence 18 and delay 33 elements are sent to information inputs / outputs of cells 1 and 2 and the recording permission signal from the output of the element OR 23 records information in selected cells 1 and 2 of drive 5, The information in the cells and 2 is recorded in the forward code, since the second inputs of the elements of Equality 18 receive a signal Log, O from the output of the element And 22 (because the input signal has not yet arrived at its input to allow the recording from output 13 of the delay). The same signal from the output of the element And 22 enters the input of the block 14 and simultaneously with the recording of information in cells 1, cell 2 records the signal Log, O, indicating that the information in cell 1 is recorded in the direct code,

Then the write enable signal, delayed by the delay element 12, through the I1Sh 11 element. It is fed to the read resolution inputs of the registers 20 and 21. During the check reading, information from the selected cells 3 and 2 is read into the registers 20 and 21 and is fed to the inputs of the corresponding elements. 25 of block 19, to the other inputs of which recording information is applied. A one-by-one comparison is made of the information recorded and read during the check reading and, if it is the same, then no information has been received.

dah of the elements 25, signals nor.J are formed, and at the output of block 19 there is a signal Log.O, indicating that there is no error in the information recorded at this address. This is where the recording process ends.

In this case, a signal appears at the input of AND 22. Log.O and the write enable signal from the output of delay element 13 does not pass to blocks 14 and 24. If the information is read from accumulator 5 in the process of controlling the information, though

: if one bit doesn’t coincide with the back of the board, it leads to an increase in the reliability of what is written into it, then at the output of block J9 and the increase in the yield of suitable chips, an error signal is generated - Log, J.

Formula

The write enable signal from the output of the delay element J3 through the AND element 22 enters the write enable inputs of blocks 14 and 24 and the second inputs of the inequality elements 18, causing the repeated recording of information in the inverse code to drive 5.

When re-recording in cell 2 Z., the signal Log. Is written, which indicates that the cells at this address store information in the inverse code.

In read mode, the decoder 3, through the amplifiers 4, unlocks the address transistors in the corresponding slots 1 and 2 of the memory. On read enable signal coming from input 9

the invention

20 Semiconductor operational back-: remembering device with information correction, containing address decoder, OR element, first and second delay elements, address groups

25 amplifiers, a drive and correction blocks, with the control inputs-outputs of each correction block connected to the information outputs of the bits of the storage group, informing the 30 OHHbie inputs and outputs of the correction blocks are the information inputs and outputs of the device; the write enable inputs of the correction blocks and the input of the first element through the OR element 11 at the inputs of the register- 35 are combined and are the input

enable recording device, the output of the first element of the holder is connected to the input of the second delay element and the first input of the element OR, the second

Ditch 20 and 21, in the latter, is found to be from information from selected ones: -: 1 and 2 memories. The signals from the output of cell 2 are received in block 17, and the ac of its output is sent to the second inputs of the elements Equality 15, the first inputs of which are signals from the registers 20. If no error signal is generated during recording, there is no re-recording and cell 2 is stored at this address Since the signal Log. O, the information from the registers 20 passes through the elements 15 to the blocks 16 without inversion. Otherwise, if the device records the output, the first element of the holder is connected to the input of the second delay element and the first input of the OR element, the second

40 whose input is a device read input, the element OR outputs are connected to read enable inputs of correction blocks, the second write enable inputs of which

45 are connected to the output of the second delay element, the addresses of the address decoder are the address inputs of the device, each output of the address decoder

connected to the inputs of the address amplifiers, the inverse of the readable cells 1 50 from this group, about the l and - information at this address.

simplify the device, in it the output

Breakdown of the gate dielectric of each address amplifier of a group of one of the address transistors whose connections are connected to the address inputs of the same name 1 or 2 creates two-bit error bits of the drive groups.

ku in the word accumulator 5, since the outputs of 1 or 2 two bits are connected to the output of each amplifier A. However, the selected cells or 2 belong to different groups of bits of accumulator 5 and the errors in them are corrected by blocks 10 independently of each other, as one-bit ones.

Connecting the output of the amplifier 4 to the inputs of several cells or 2 leads to a simplification of the device and the umanshenryp area of the crystal, and reducing the number of elements and the area of the invention

Semiconductor operational back-: remembering device with information correction, containing address decoder, OR element, first and second delay elements, address groups

amplifiers, a drive and correction blocks, with the control inputs-outputs of each correction block connected to the information outputs of the bits of the storage group, the information OHHbie inputs and outputs of the correction blocks are information inputs and outputs of the device; correction blocks and the input of the first element 35 are combined and are the input

enable recording device, the output of the first element of the holder is connected to the input of the second delay element and the first input of the element OR, the second

40 whose input is a device read input, the element OR outputs are connected to read enable inputs of correction blocks, the second write enable inputs of which

45 are connected to the output of the second delay element, the inputs of the address decoder are the address inputs of the device, each output of the address decoder

Claims (1)

Claim Semiconductor operational memory correction device containing an address decoder, an OR element, first and second delay elements, groups of addressable amplifiers, a drive and correction blocks, the control inputs and outputs of each correction block connected to the information outputs of the bits of the drive group, information inputs and outputs correction blocks are information inputs and outputs of the device, and the first recording permission inputs of correction blocks and the input of the first delay element are combined and are the resolution input recording device, the output of the first delay element is connected to the input of the second delay element and the first input of the OR element, the second input of which is the read permission input of the device, the outputs of the OR element are connected to the read permission inputs of correction blocks, the second recording permission inputs of which are connected to the output of the second element delays, the addresses of the address decoder are the address inputs of the device, each output of the address decoder is connected to the inputs of the address amplifiers of the corresponding group, then, to simplify the apparatus, it output amplifier of each address group is connected to address inputs of similar digits storage groups. ВНИИПИ Order 6085/53 ___ Circulation 590 Subscription Custom polygr. ave, city of Uzhhorod, st. Project, 4