SU1432524A1 - Device for monitoring the operation of keys of composition field - Google Patents

Abstract

The invention relates to automation and computing and can be used to monitor the execution of operations, for example, in control systems, in simulators for training control system operators. The aim of the invention is to expand

Description

CwuSfCi

ate

capabilities of the device, reducing the operator's load and increasing the efficiency of its work in the formation of arrays of information. The device contains blocks of constant 1 and random-access memory 5, register 2, code transfer block 3, RS-flip-flops, counters 9 and 10, switch block 6, pulse drivers, element OR 8, multiplexer 14, decoder 24, distribution block 42- pulses, consisting of the distributor 25 and the major element 27, the delay element and the elements 20-23, 13,33,29 and 30. With the help of multiplexer 14 and counter 10, the keys 15 and 16 of the typing field are polled, addresses are generated numbers of pressed keys 15 (16), and in block 5 of the memory at these addresses is recorded Signals are coming

logical units. At the end of the codogram collection, the distributor 25 is turned on, the signals of which read the logical units from the RAM block 5. The addresses are given by the counter 9 and are fixed in register 2 in each subsequent clock cycle. The counter is 9 and. Register 2 form the address of the G block of the permanent memory. In block 1 of the permanent memory at the addresses corresponding to the given set of keys 15 (16) of the typing field, the signals of logical units are pre-recorded. When the operator acts correctly, the signals of logical units are recorded from the constant memory block 1 by the addresses specified by the register 2 and the counter 9, which are fixed by the trigger 17. In the absence of these signals, an error signal is generated. 3 il.

one

The invention relates to automation and computing and can be used to monitor the execution of operations, for example, in control devices.

The purpose of the invention is to increase the reliability of the device operation by determining the belonging of the affected keys on the field to the transmitted message.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a control block diagram; Fig, 3 is a diagram of the distributor.

The device contains a fixed memory block 1, a register 2, a code transfer block 3, a fifth RS flip-flop 4, a RAM block 5, a switch block 6, a control block 7, an OR element 8, a second 9 and the first 10 counters, the first pulse generator 11 (on the falling edge), the first RS flip-flop 12, the third element AND 13, multiplexer 14, keys 15 and 16 of the keypad, and the keys 15 are the message set keys and the key 16 is the message input first D -trigger 17, fourth RS-trigger 18, generator 19 pulses, seventh 20, six

21, first 22 and fifth 23 elements And, decoder 24, distributor 25, second element AND 26, major element 27, second RS flip-flop 28, eighth 29 and ninth 30 And elements, second D-flip-flop 31 , the sixth RS trigger 32, and the fourth element And 33.

The device also contains (FIG. 2) a third RS flip-flop 34, a second pulse shaper 35 (on a leading edge), a delay element 36 and a third pulse shaper 37 (on a falling edge), forming a control block 7.

The distributor (FIG. 3) consists of a counter 38, a decoder 39, a switch 40 and a delay element 41.

The distributor 25 and the major element 27 form a pulse distribution unit 42.

The keys 15 are structurally grouped into groups, each of which is intended for a set of a specific message — codograms. The sequence of pressing the keyboard in this group is arbitrary, however, the keys of other groups should not be pressed or the keys of this group should be skipped, which indicates an operator error. The codogram is output to an external device after it has been typed by the operator by pressing the 16 Enter key.

The operation of the device consists of three modes.

In the first mode, the pressed keys 15 are remembered. For this, the addresses 34, the trigger 34 are assigned to the addresses corresponding to the codes.

My keys 15, in block 5, the signals are recorded Log, 1.

In the second mode, which is activated by pressing the Enter key, analy-. The belonging of the pressed keys 15 to this group is determined. Dp of this, sequential reading of signals from all cells of block 5 and the formation of addresses for block 1 corresponding to the codes of the keys selected by the operator are carried out. In block 1 of constant memory, the predetermined (correct) addresses corresponding to the key codes of this group are pre-recorded at the front of the potential signal of the trigger 34, the driver 33 outputs a pulse to the control input CS of the block 5. The signal is recorded

15 Log.1 at the address specified by the TO counter and the corresponding key code. The same impulse through element 36 zeroes the trigger 34, while at the output of the imager 37 for20 a pulse is pulsed, which zero the trigger 12 and the counter 10. Counter 10 is turned on for counting the clock pulses and again cyclically polling the keys 15 before pressing the next scheduled signal. Reading of these signals. Similarly, for all other nanals from block 1, it indicates the correctness of the set; the absence of at least one indicates an error. After this analysis, the device switches to the third mode, the zeroing mode of block 5 to prepare the device for the next message set.

In the initial state, counters 9 and 10, triggers 4, 12, 17, 18, 28, 31,

40

Operator-pressed keys 15 in block 5 at the corresponding addresses are logged. Log.1.

After pressing all the required keys, the operator presses the key 16

Enter to display a typed message to an external device. In this case, the trigger 32 is set to one. The trigger 32 has been prepared32 and the FOR is in the zero state 35, the opening element is AND 33. For (zero means are not shown). The trigger 18 supplies the control input W / R of the block 5 with a potential zero signal from its direct output, which corresponds to the mode of recording information in block 5, and connects the zero signal through the block 6 to the address inputs of block 5 to the outputs of the counter 10. The trigger 28 supplies to information D-input of the block 5 potential with a single potential on the control signal from the inverse output and the input W / R of the block 5 and connects through

The block 6 of the counter 9 outputs to the address inputs of the block 5. The trigger 28 sends a zero signal to the information D- input of the block 5 and closes the AND 13 element, turns off the counters 10 from the generator 19 and allows its clock pulses to be passed through the AND 26 element to the clock input of the distributor 25 .

at the corresponding position, the counter gg. The distributor 25 operates the cyclical 10, at the output of the multiplexer 14 it generates a signal which sets the trigger 12 in one state. The trigger 12 stops the counter

The key code 16, like other keys, also records the signal Lgg in block 5. After that, the pulse from the output of the imager 37 also zeroes trigger 12, counter 10 and, through element 33, it sets the triggers 18 and 28 to one state.

The trigger 18 sets the reading mode to express the supply of clock pulses from the output of the generator 19 through the element 13 to the counting input of the counter 10. The codes from the outputs of the counter 10 are fed to the address inputs of the multiplexer 14, with which the keys 15 are cyclically polled.

When the operator presses the keys 15,

50

control pulses and performs a cycle of reading one cell of block 5. The signal from the first output of the distribution

10 by removing the control signal from its input. The counter code 10 is the key pressed code and is fed through block 6 to the address inputs of block 5.

After the operator has released the pressed key 15, the former 11 generates a pulse along the trailing edge, which through the element OR 8 sets

leading edge of a potential sig. the trigger trigger 34, the driver 33 outputs a pulse to the control input CS of the block 5. A signal is recorded

Log.1 at the address specified by the TO counter and the corresponding key code. The same impulse through the element 36 zeroes the trigger 34, and a pulse is formed at the output of the imager 37, which zeroes the trigger 12 and the counter 10. The counter 10 is turned on for counting the clock pulses and again cyclically polls the keys 15 until the next key is pressed

  opening element 33. For a potential, at the control input of the W / R unit 5 and connects through

The key code 16, like other keys, also records the signal Lgg in block 5. After that, the pulse from the output of the imager 37 also zeroes trigger 12, counter 10 and, through element 33, it sets the triggers 18 and 28 to one state.

Trigger 18 sets the reading mode for you50.

 The distributor 25 operates cyclically and in each cycle forms a

control pulse and performs a cycle of reading one cell of block 5. The signal from the first output of the distributor 25 through the element OR 8 includes block 7, which reads information from the cells of block 5 to the addresses specified by the counter 9. When the counter code 9 corresponds to the code key 15, the output of block 5 reads the signal Log.1, which sets the trigger 4 in one state. The latter allows the delivery of the counter code 9 through block 3 to the information inputs of register 2 and one address inputs of block 1. In addition addition trigger 4 bit prevents passage through the elements And 22 and 23 of the second and third control signals of the distributor 25.

Counter code 9 together with register code 2, the code of which is fed to other address inputs of block 1, form the full address of block 1, and in register 2 the counter code 9 of the previous cycle is stored in the current cycle - no single signal from block 5. In block 1, the constant memory by the addresses that correspond to the sequence of key codes of this particular: group, the signals are prerecorded: LoG.1. For example, if this group of keys includes the number keys

1,3,5, then the DL addresses of Log.1 are formed as follows: the first; the address is 01, the second address is 13, thr; The address is 35, where the first digit of the address is the code in register 2, and the second digit of the address is the code in counter 9. Log.O. signals are recorded at other addresses (00,10,30, etc.).

Thus, if the operator

ten

15

0

25

thirty

35

the stroke of the distributor 25 in this cycle is fed to the first input of the element 27, to the second input of which the clock pulses from the output of the element 26 enter. The element 27 opens when two input signals from tp fall and self-blocks along the feedback circuit, which ensures complete passage through it a clock pulse after zeroing the distributor 2. The signal from the output of the element 27 zeroes the distributor 25 and the trigger 4 increases the contents of counter 9 by one and interrogates the element 30.

After zeroing, the distributor 2 starts the next cycle and the operation of the device repeats. In the case of incorrectly selected by the operator key addresses at the inputs of block 1, formed by the counter 9 and register 2, n correspond to the addresses at which Log.1 signals are recorded in block 1. Therefore, the trigger 17 is set to zero position by a signal from the output and the element. E 23, a. the signal from the output of the element And 22 reads through the element And 20 the error signal, which is transmitted to an external device. /

After going through the entire given address list pL, the estimator 9 is set to the position in which the decoder 2 carries the signal, sets the 1st state to the counting trigger 31 The trigger 31 prepares the AND 30 element to open and closes the 29 E element. distribution 25 a signal from the output of the element 27 through the element And 30 zeroed trig

After the reset of the Vishi of this group of keys was selected correctly, the required key is 40 R, then with trigger 18, the cyclic reading of information from the W / R block 5 is set to the control input

unit 5 in the corresponding work cogs of the distributor 25 at the output of block 1 a single signal is generated, which is fed to the information input of the trigger 17. The pulse from the second output of the distributor 25 in this cycle through the element 23 and the trigger 17 is set to one state, which indicates that the key whose code is analyzed in a given cycle, the desired group of keys. The trigger 17 closes the element And 20. The signal from the third output of the distributor. 25 in this cycle through the element And 22 polls the element And 20 and rewrites the code of the counter 9 in the register 2. The signal from the fourth high

five

0

five

0

five

the stroke of the distributor 25 in this cycle is fed to the first input of the element; 27, the second input of which receives the clock pulses from the output of element AND 26. Element 27 opens when two of the three input signals coincide and blocks itself in a reverse circuit. connection, which ensures that the clock pulse passes through it after the zeroing of the distributor 25. The signal from the output of the element 27 embraces the distributor 25 and the trigger 4 increases the contents of the counter 9 by one and polls the And 30 element.

After zeroing, the valve 25 starts the next cycle and the operation of the device repeats. In the case of incorrectly selected by the operator keys, the addresses at the inputs of block 1, formed by the counter 9 and register 2, do not correspond to the addresses at which Log.1 signals are recorded in block 1. Therefore, the trigger 17 is set to the zero position by a signal from the output of the element E 23, a. the signal from the output of the element And 22 reads through the element And 20 an error signal, which is transmitted to an external device. /

After iterating through the entire specified address field, the estimator 9 is set to the position in which the decoder 24 carries the signal, setting the 1st trigger counting element 31 to one. The trigger 31. prepares the AND 30 element for opening and closes the AND 29 element. the signal from the output of the element 27 through the element And 30 zeroed trig

records In this case, the information D-input of block 5 is supplied with a zero trigger signal 28. After the zeroing is completed, the valve 25 is turned on again and the signals from its first and fourth outputs record Log.O signals to all cells of the memory block 5. After iterating over the (secondary) entire address field by the counter 9, the decoder 24 again outputs a signal that sets the counting trigger 31 to the zero state. In this case, the element 29 is prepared for opening and at the end of this cycle it is opened by a signal from the output of the element 27. The signal from the output of the element 29 has reset the triggers 28, 32 and

And 21 in the case of the single state of the trigger 17, the Input signal is enabled to the external device. Thus, the device inserts the verified message into the external device and is reset to the new set of the next message,

The device provides control of the accessories of the operator’s controls to this message, which expands the capabilities of the device, reduces the operator’s psychological burden, reduces the number of errors in the operator’s actions, and thereby shortens the inLormadai set time.

Claims (1)

Invention Formula Device for ontrol control of keys of a keypad, containing a block of permanent memory, a register, two D-flip-flops, a decoder, an OR element, the first and second counters, the first And element, the first pulse shaper, the first RS-trigger, pulse generator and a multiplexer whose information inputs are input device inputs for connecting the keypad to the monitored keys, and the group of address inputs is connected to the output group of the first counter connected by the account resolution input to the inverse output of the first RS flip-flop, the S input of which is connected to the multiplexer output connected through the first pulse generator the first input of the OR element, the register output group is connected to the group of the first address inputs of the fixed memory unit, and the control input is connected to the output of the first AND element, characterized in that You can increase the reliability of the device by determining the belonging of the keys of the keypad to the message field, a code transmission block, a random access memory block, a switching block, a pulse distribution block, the second and third pulse formers, and a delay element from the second to the sixth are entered into it. RS-triggers and from the second to the ninth elements And, the output of the pulse generator is connected to the first inputs of the second and third elements And, the second; which inputs are connected to the direct 0 five 0 five 0 five 0 five 0 and inverse outputs, respectively, of the second RS flip-flop, and outputs, respectively, to the input of the pulse distribution unit and the counting input of the first counter, connected by a reset input to the first input of the fourth element And, the R input of the first RS-trigger and the output of the third pulse shaper, whose input connected to the direct output of the third RS-flip-flop and through the second pulse shaper - to. the input of the delay element and to the first control input of the operative memory block, connected by the second control input with the control input of the switching unit and with the direct output of the fourth RS flip-flop, the information input with the inverse output of the second flip-flop, the address group inputs — with the output unit of the switching unit, and output — with the 8th input of the fifth RS flip-flop, the direct output of which is connected to the control input of the code transmission unit and to the first inputs of the first and fifth elements I, the output group of the first counter is connected to groups the first information inputs of the switching unit, the group of second information inputs of which are connected to the output group of the second counter, the input group of the decoder, and the information input group of the code transmission unit associated with the output group with the group of installation inputs of the register and the second address input group of the permanent memory block These outputs are connected to the D input of the first D flip-flop a connected to the direct and inverse outputs to the first inputs of the sixth and seventh And elements, respectively, whose outputs are respectively, the output of the correct operation and the output of the key operation error of the keypad, the output of the first element I is connected to the second input of the seventh element I, the output of the fifth element I to the C input of the first D flip-flop, the output of the eighth element I to the R inputs of the second and of the sixth RS trigger and with the second input of the sixth element I, and the output of the ninth element I with the R input of the fourth RS-trigger-. the second and second reset inputs are connected to the decoder output, the D input to its inverse output, and the forward and inverse outputs to the first inputs of the ninth and eighth elements. And, the inverse output the fourth RS flip-flop is connected to the second input of the eighth And element, and the direct output of the sixth RS flip-flop is connected to the second input of the fourth And element connected by the output to the S-input of the second and fourth RS-trcggers, the output of the OR element: single with S- the input of the third RS-flip-flop, -the first output of the block distribution Neither I1 1 DulSop connected to the second input of the OR element, the second and third outputs to the second inputs of the fifth and first elements AND, respectively, and the fourth output to the third input of the eighth element AND, the second input of the ninth element AND, the counting input of the second counter and the R input of the fifth RS flip-flop, the S-input of the sixth RS flip-flop being connected to one of the information inputs of the device.